PDF ADS1606 Data sheet ( Hoja de datos )

Número de pieza	ADS1606
Descripción	16 BIT 5MSPS ANALOG TO DIGITAL CONVERTER
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ADS1605 ADS1606 SBAS274E − MARCH 2003 − REVISED JUNE 2004 16ĆBit, 5MSPS AnalogĆtoĆDigital Converter FEATURES D Data Rate: 5MSPS (10MSPS in 2X Mode) D Signal-to-Noise Ratio: 88dB D Total Harmonic Distortion: −99dB D Spurious-Free Dynamic Range: 101dB D Linear Phase with 2.45 MHz Bandwidth D Passband Ripple: ±0.0025dB D Selectable On-Chip Reference D Directly Connects to TMS320C6000 DSPs D Easily Upgradable to 18 Bits with the ADS1625 and ADS1626 D Adjustable Power Dissipation: 315 to 570mW D Power Down Mode D Supplies: Analog +5V Digital +3V Digital I/O +2.7 to +5.25V APPLICATIONS D Scientific Instruments D Automated Test Equipment D Data Acquisition D Medical Imaging D Vibration Analysis DESCRIPTION The ADS1605 and ADS1606 are high-speed, high-precision, delta-sigma analog-to-digital converters (ADCs) with 16-bit resolution. The data rate is 5 mega-samples per second (MSPS), the bandwidth (−3dB) is 2.45MHz, and passband ripple is less than ±0.0025dB (to 2.2MHz). Both devices offer the same outstanding performance at these speeds with a signal-to-noise ratio up to 88dB, total harmonic distortion down to −99dB, and a spurious-free dynamic range up to 101dB. For even higher-speed operation, the data rate can be doubled to 10MSPS in 2X mode. The ADS1606 includes an adjustable first-in first-out buffer (FIFO) for the output data. The input signal is measured against a voltage reference that can be generated on-chip or supplied externally. The digital output data is provided over a simple parallel interface that easily connects to digital signal processors (DSPs). An out-of-range monitor reports when the input range has been exceeded. The ADS1605/6 operate from a +5V analog supply (AVDD) and +3V digital supply (DVDD). The digital I/O supply (IOVDD) operates from +2.7 to +5.25V, enabling the digital interface to support a range of logic families. The analog power dissipation is set by an external resistor and can be reduced when operating at slower speeds. A power down mode, activated by a digital I/O pin, shuts down all circuitry. The ADS1605/6 are offered in a TQFP-64 package using TI PowerPAD technology. The ADS1605 and ADS1606, along with their 18-bit counterparts, the ADS1625 and ADS1626, are well suited for the demanding measurement requirements of scientific instrumentation, automated test equipment, data acquisi- tion, and medical imaging. VREFP VREFN VMID RBIAS VCAP AVDD DVDD IOVDD Reference and Bias Circuits AINP AINN DS Modulator ADS1605 ADS1606 AGND Digital Filter I/O Interface ADS1606 Only FIFO DGND PD REFEN RESET CLK CS 2XMODE RD DRDY OTR DOUT[15:0] FIFO_LEV[2:0] Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright  2003−2004, Texas Instruments Incorporated www.ti.com 1 page www.ti.com ADS1605 ADS1606 SBAS274E − MARCH 2003 − REVISED JUNE 2004 ELECTRICAL CHARACTERISTICS (continued) All specifications at −40°C to +85°C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, 2XMODE = low, VCM = 2.0V, FIFO disabled, and RBIAS = 37kΩ, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Voltage Reference(1) VREF = (VREFP − VREFN) VREFP 2.5 3.0 3.2 V 3.75 4.0 4.25 V VREFN 0.75 1.0 1.25 V VMID 2.3 2.5 2.8 V VREF drift Startup time Internal reference (REFEN = low) Internal reference (REFEN = low) 50 ppm/°C 15 ms Clock Input Frequency (fCLK) Duty Cycle Digital Input/Output fCLK = 40MHz 40 50 MHz 45 55 % VIH VIL VOH VOL Input leakage IOH = 50µA IOL = 50µA DGND < VDIGIN < IOVDD 0.7 IOVDD DGND IOVDD − 0.5 IOVDD 0.3 IOVDD DGND +0.5 ±10 V V V V µA Power-Supply Requirements AVDD 4.75 5.25 V DVDD 2.7 3.3 V IOVDD 2.7 5.25 V AVDD current (IAVDD) REFEN = low REFEN = high 110 135 mA 85 105 mA DVDD current (IDVDD) IOVDD current (IIOVDD) Power dissipation IOVDD = 3V AVDD = 5V, DVDD = 3V, IOVDD = 3V, REFEN = high PD = low, CLK disabled 45 55 mA 4 6 mA 570 710 mW 5 mW Temperature Range Specified −40 +85 °C Operating −40 +105 °C Storage −60 +150 °C Thermal Resistance, θJA θJC PowerPAD soldered to PCB with 2oz. trace and copper pad. 25 °C/W 0.5 °C/W (1) The specification limits for VREF, VREFP, VREFN, and VMID apply when using the internal or an external reference. The internal reference voltages are bounded by the limits shown. When using an external reference, the limits indicate the allowable voltages that can be applied to the reference pins. 5 5 Page www.ti.com CLK RESET DRDY RD t11 t9 t23 t25 t24 ADS1605 ADS1606 SBAS274E − MARCH 2003 − REVISED JUNE 2004 t26 Figure 6. Reset Timing (ADS1606 with FIFO Enabled) TIMING REQUIREMENTS FOR FIGURE 6 SYMBOL DESCRIPTION t9 RESET pulse width t11 RESET rising edge to falling edge of CLK t23 RD pulse low after RESET goes high t24 RD pulse high before first DRDY pulse after RESET goes high t25 DRDY low after RESET goes low t26 Delay from RESET high to valid DOUT (settling to 0.001%) MIN TYP MAX UNIT 50 ns −5 10 ns 8 CLK Cycles 8 CLK Cycles 8 × (FIFO level + 1) CLK Cycles See Table 4 DRDY Cycles 11 11 Page

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