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PDF ADV7197 Data sheet ( Hoja de datos )
| Número de pieza | ADV7197 | |
| Descripción | Multiformat HDTV Encoder with Three 11-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Multiformat HDTV Encoder with
Three 11-Bit DACs
ADV7197
FEATURES
INPUT FORMATS
YCrCb in 2 ؋ 10-Bit (4:2:2) or 3 ؋ 10-Bit (4:4:4) Format
Compliant to SMPTE274M (1080i), SMPTE296M
(720p) and Any Other High-Definition Standard Using
Async Timing Mode
RGB in 3 ؋ 10-Bit 4:4:4 Format
OUTPUT FORMATS
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit + Sync (DAC A)
11-Bit DACs (DAC B, C)
PROGRAMMABLE FEATURES
Internal Test Pattern Generator with Color Control
Y/C Delay (؎)
Individual DAC On/Off Control
VBI Open Control
I2C Filter
2-Wire Serial MPU Interface
Single Supply 5 V/3.3 V Operation
52-Lead MQFP Package
APPLICATIONS
HDTV Display Devices
HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction
Y0–Y9
Cr0–Cr9
Cb0–Cb9
CLKIN
HORIZONTAL
SYNC
VERTICAL
SYNC
BLANKING
RESET
FUNCTIONAL BLOCK DIAGRAM
TEST
PATTERN
GENERATOR
AND
DELAY
CHROMA
4:2:2 TO 4:4:4
(SSAF)
CHROMA
4:2:2 TO 4:4:4
(SSAF)
11-BIT
+ SYNC
DAC
11-BIT
DAC
11-BIT
DAC
SYNC
GENERATOR
TIMING
GENERATOR
DAC CONTROL
BLOCK
I2C MPU
PORT
ADV7197
DAC A (Y)
DAC B
DAC C
VREF
RSET
COMP
GENERAL DESCRIPTION
The ADV7197 is a triple, high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.
The ADV7197 has three separate 10-bit-wide input ports that
accept data in 4:4:4 10-bit YCrCb or RGB, or 4:2:2 10-bit
YCrCb. This data is accepted in HDTV format at 74.25 MHz
or 74.1758 MHz. For any other high definition standard but
SMPTE274M or SMPTE296M, the Async Timing Mode can
be used to input data to the ADV7197. For all standards,
external horizontal, vertical, and blanking signals or EAV/SAV
codes control the insertion of appropriate synchronization signals
into the digital data stream and therefore the output signals.
The ADV7197 outputs analog YPrPb HDTV complying to
EIA-770.3, or RGB complying to RS-170/RS-343A.
The ADV7197 requires a single 5 V/3.3 V power supply, an
optional external 1.235 V reference, and a 74.25 MHz (or
74.1758 MHz) clock.
The ADV7197 is packaged in a 52-lead MQFP package.
*ADV is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
ADV7197
3.3 V TIMING–SPECIFICATIONS (VAA = 3.15 V to 3.45 V, VREF = 1.235 V, RSET = 2470 ⍀, RLOAD = 300 ⍀. All specifications
TMIN to TMAX [0؇C to 70؇C] unless otherwise noted.)
Parameter
Min Typ Max Unit
Conditions
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulsewidth, t1
SCLOCK Low Pulsewidth, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
10
0.6
1.3
0.6
0.6
100
0.6
100
400 kHz
µs
µs
µs
µs
ns
300 ns
300 ns
µs
ns
After This Period the 1st Clock Is Generated
Relevant for Repeated Start Condition
ANALOG OUTPUTS2
Analog Output Delay
Analog Output Skew
10 ns
0.5 ns
CLOCK CONTROL AND PIXEL PORT3
fCLK
tCLK
Clock High Time, t9
Clock Low Time, t10
Data Setup Time, t11
Data Hold Time, t12
Control Setup Time, t11
Control Hold Time, t12
Pipeline Delay
74.25 MHz
HDTV Mode
81 MHz
Async Timing Mode
5 1.5
ns
5 2.0
ns
2.0 ns
4.5 ns
7 ns
4.0 ns
16 Clock Cycles For 4:4:4 Pixel Input Format
NOTES
1Guaranteed by characterization.
2Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3Data: Cb/Cr (9:0), Cr (9:0), Y (9:0); Control: HSYNC/SYNC, VSYNC/TSYNC; DV
Specifications subject to change without notice.
CLOCK
t9 t10
Y0 Y1 Y2
...
...
Yxxx
Yxxx
PIXEL INPUT
DATA
Cb0
t12
t11
Cr0
Cb1
Cr1
...
Cbxxx
Crxxx
Figure 1. 4:2:2 Input Data Format Timing Diagram
t9 – CLOCK HIGH TIME
t10 – CLOCK LOW TIME
t11 – DATA SETUP TIME
t12 – DATA HOLD TIME
REV. 0
–5–
5 Page 
ADV7197
A Logic “0” on the LSB of the first byte means that the master
will write information to the peripheral. A Logic “1” on the LSB
of the first byte means that the master will read information
from the peripheral.
The ADV7197 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses
plus the R/W bit. It interprets the first byte as the device address
and the second byte as the starting subaddress. The subaddresses
auto-increment, allowing data to be written to or read from the
starting subaddress. A data transfer is always terminated by a
Stop condition. The user can also access any unique subad-
dress register on a one-by-one basis without having to update
all the registers.
Stop and Start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCL high period the
user should issue only one Start condition, one Stop condition
or a single Stop condition followed by a single Start condition. If
an invalid subaddress is issued by the user, the ADV7197 will
not issue an acknowledge and will return to the idle condition. If
in auto-increment mode, the user exceeds the highest subaddress,
the following action will be taken:
1. In Read Mode, the highest subaddress register contents
will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A no-
acknowledge condition is where the SDA line is not pulled
low on the ninth pulse.
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7197 and the part will return to the idle
condition.
SDATA
SCLOCK S 1–7 8 9
1–7 8 9
START ADDR R/W ACK SUBADDRESS ACK
1–7 8 9
P
DATA
ACK STOP
Figure 9. Bus Data Transfer
Figure 9 illustrates an example of data transfer for a read
sequence and the Start and Stop conditions.
Figure 10 shows bus write and read sequences.
REGISTER ACCESSES
The MPU can write to or read from all of the registers of the
ADV7197 except the Subaddress Registers, which are write-only
registers. The Subaddress Register determines which register is
accessed by the next read or write operation.
All communications with the part through the bus begin with an
access to the Subaddress Register. A read/write operation is
performed from/to the target address which then increments to
the next address until a Stop command on the bus is performed.
REGISTER PROGRAMMING
The following section describes the functionality of each regis-
ter. All registers can be read from as well as written to unless
otherwise stated.
Subaddress Register (SR7–SR0)
The Communications Register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress is set up. The Subaddress
Register determines to/from which register the operation
takes place.
Figure 11 shows the various operations under the control of the
Subaddress Register. “0” should always be written to SR7.
Register Select (SR6–SR0)
These bits are set up to point to the required starting address.
WRITE
SEQUENCE
S SLAVE ADDR A(S)
SUB ADDR
A(S)
LSB = 0
DATA
A(S)
LSB = 1
DATA
A(S) P
READ
SEQUENCE
S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S)
DATA
A(M)
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER A(M) = NO-ACKNOWLEDGE BY MASTER
DATA
Figure 10. Write and Read Sequence
A(M) P
SR7 SR6 SR5
SR4 SR3 SR2 SR1 SR0
SR7
ZERO SHOULD
BE WRITTEN
HERE
ADDRESS
00h
01h
02h
03h
04h
05h
06h
07h
08h
ADV7197 SUBADDRESS REGISTER
SR6 SR5 SR4 SR3 SR2 SR1 SR0
00 0 0 0 0 0
00 0 0 0 0 1
00 0 0 0 1 0
00 0 0 0 1 1
00 0 0 1 0 0
00 0 0 1 0 1
00 0 0 1 1 0
00 0 0 1 1 1
00 0 1 0 0 0
MODE REGISTER 0
MODE REGISTER 1
MODE REGISTER 2
MODE REGISTER 3
MODE REGISTER 4
MODE REGISTER 5
COLOR Y
COLOR CR
COLOR CB
Figure 11. Subaddress Registers
REV. 0
–11–
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