PDF MPC974 Data sheet ( Hoja de datos )

Número de pieza	MPC974
Descripción	3.3V PLL Clock Driver
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V PLL Clock Driver The MPC974 is a fully integrated PLL based clock generator and clock distribution chip which operates from a 3.3V supply. The MPC974 is ideally suited for high speed, timing critical designs which need a high level of clock fanout. The device features 15 high drive LVCMOS outputs, each output has the capability of driving a 50Ω parallel terminated transmission line or two 50Ω series terminated transmission lines on the incident edge. • Fully Integrated PLL • Two Reference Clock Inputs for Redundant Clock Applications • High Impedance Output Control • Logic Enable on the Outputs • 3.3V VCC Supply • Output Frequency Configurable • TQFP Packaging • ±100ps Typical Cycle–to–Cycle Jitter MPC974 LOW VOLTAGE PLL CLOCK DRIVER The MPC974 features 3 independent frequency programmable banks of outputs. The frequency programmability offers the capability of establishing output frequency relationships of 1:1, 2:1, 3:1, 3:2 and 3:2:1. In addition, the device features a separate feedback output which allows for a wide variety of input/output frequency multiplication alternatives. The VCO_Sel pin provides an extended VCO lock range for added flexibility and general purpose usage. The TCLK0 and TCLK1 inputs provide a method for dynamically switching the PLL between two different clock sources. The PLL has been optimized to provide small deviations in output pulse width and well controlled, slow transition back to lock when the inputs are switched between two references that are equal in frequency but out of phase with each other. This feature makes the MPC974 an ideal solution for fault tolerant applications which require redundant clock sources. FA SUFFIX 52–LEAD TQFP PACKAGE CASE 848D-03 All of the control pins are LVTTL/LVCMOS level inputs. The Fsel pins control the VCO divide ratios that are applied to the various output banks and the feedback output. The MR input will reset the internal flip flops and place the outputs in high impedance when driven LOW. The OE pin will force all of the outputs except the feedback output LOW to allow for acquiring phase lock prior to providing clocks to the rest of the system. Note that the OE pin is not synchronized to the internal clock. As a result, the initial pulse after de–assertion of the OE pin may be distorted. The PLL_En pin allows the PLL to be bypassed for board level functional test. When bypassed the signal on the selected TCLK will be routed around the PLL and will drive the internal dividers directly. The MPC974 is packaged in the 52–lead TQFP package to provide optimum electrical performance as well as minimize board space requirements. The device is specified for 3.3V VCC. 1/97 © Motorola, Inc. 1997 1 REV 2 1 page 33MHz TCLK FB_In 5 Qa 5 Qb 4 Qc QFB 66MHz 66MHz 33MHz 33MHz fsela fselb fselc fselFB VCO_Sel 0 0 0 00 0 MPC974 33MHz TCLK FB_In 5 Qa 5 Qb 4 Qc QFB 100MHz 50MHz 33MHz 33MHz fsela fselb fselc fselFB VCO_Sel 0 1 1 10 0 25MHz TCLK FB_In 5 Qa 5 Qb 4 Qc QFB 100MHz 50MHz 33MHz 25MHz fsela fselb fselc fselFB VCO_Sel 0 1 1 01 0 50MHz TCLK FB_In 5 Qa 5 Qb 4 Qc QFB 50MHz 50MHz 50MHz 50MHz fsela fselb fselc fselFB VCO_Sel 1 1 0 00 0 Figure 3. MPC974 Programming Schemes To minimize part–to–part skew the external feedback option again should be used. The PLL in the MPC974 decouples the delay of the device from the propagation delay variations of the internal gates. From the specification table one sees a Tpd variation of only ±150ps, thus for multiple devices under identical configurations the part–to–part skew will be around 850ps (300ps for Tpd variation plus 350ps output–to–output skew plus 200ps for jitter). To minimize this value, the highest possible reference frequencies should be used. Higher reference frequencies will minimize both the tpd parameter as well as the input to output jitter. Power Supply Filtering The MPC974 is a mixed analog/digital product and exhibits some sensitivities that would not necessarily be seen on a fully digital product. Analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. The MPC974 provides separate power supplies for the output buffers (VCCO) and the internal PLL (VCCA) of the device. The purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase–locked loop. In a controlled environment such as an evaluation board this level of isolation is sufficient. However, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simplest form of isolation is a power supply filter on the VCCA pin for the MPC974. 3.3V RS=5–15Ω VCCA MPC974 0.01µF 22µF VCC 0.01µF Figure 4. Power Supply Filter Figure 4 illustrates a typical power supply filter scheme. The MPC974 is most susceptible to noise with spectral content in the 1KHz to 1MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin of the MPC974. From the data sheet the IVCCA current (the current sourced through the VCCA pin) is typically 15mA (20mA maximum), assuming that a minimum of 3.0V must be maintained on the VCCA pin very little DC voltage drop can be tolerated when a 3.3V VCC supply is used. The resistor shown in Figure 4 must have a resistance of 10–15Ω to meet TIMING SOLUTIONS BR1333 — Rev 6 5 MOTOROLA 5 Page

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