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ISL12023 Datasheet PDF - Intersil

Part Number ISL12023
Description Low Power RTC
Manufacturers Intersil 
Logo Intersil Logo 

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ISL12023 datasheet, circuit
Low Power RTC with Battery-Backed SRAM andNOc1NTo-8nOR8taE8Rc-CEItNOCoTMOuErMMRTMESeNIcELhDNonEDriDcEwaDFlwOSRwRuE.ipPnNpLtEeoArWrsCt iCElD.ceMEonSEmtIeNG/rTtNsacSt
DATASHEET
Embedded Temp Compensation ±5ppm with Auto
Daylight Saving
ISL12023
The ISL12023 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brownout
indicator, single periodic or polled alarms, intelligent
battery-backup switching, Battery Reseal™ function and 128
bytes of battery-backed user SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically, using
parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
VBAT power, and also from VBAT to VDD power.
Applications
• Utility Meters
• POS Equipment
• Medical Devices
• Security Systems
• Vending Machines
• White Goods
• Printers and Copiers
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating Temp
Range
- ±5ppm Over -40°C to +85°C
• 10-bit Digital Temperature Sensor Output
- ±2°C Accuracy
• Customer Programmable Day Light Saving Time
• Clock Output with 15 Selectable Frequencies
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Battery Reseal™ Function to Extend Battery Shelf Life
• Automatic Backup to Battery or Super Capacitor
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor
- 2 User Programmable Levels
• Seven Selectable Voltages for Each Level
• Power Status Brownout Monitor
- Six Selectable Trip Levels, from 2.295V to 4.675V
• Oscillator Failure Detection
• Time Stamp for First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• Separate FOUT, IRQ, and LVRST Outputs
• I2C Bus™
- 400kHz Clock Frequency
• 14 Ld TSSOP Package
• Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL12023IVZ
12023 IVZ
2.7 to 5.5
-40 to +85
14 Ld TSSOP
M14.173
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
December 6, 2011
FN6682.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. I2C Bus™ is a trademark
owned by NXP Semiconductors Netherlands, B.V. All other trademarks mentioned are the property of their respective owners.

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ISL12023 equivalent
ISL12023
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 11)
TYP MAX
(Note 7) (Note 11)
UNITS NOTES
tDH Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters
the 30% to 70% of VDD window.
0
tR SDA and SCL Rise Time
From 30% to 70% of VDD.
20 + 0.1 x Cb
tF SDA and SCL Fall Time
From 70% to 30% of VDD.
20 + 0.1 x Cb
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
300
300
400
ns
ns 10
ns 10
pF 10
RPU SDA and SCL Bus Pull-up Resistor Off- Maximum is determined by tR
chip and tF.
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
1
k10
NOTES:
4. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT<1.8V.
5. IRQ/FOUT Inactive.
6. VDD > VBAT +VBATHYS
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Limits should be considered typical and are not production tested.
10. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
12. Specifications are typical and require using a recommended crystal (see “Application Section” on page 24).
13. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested.
14. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
Submit Document Feedback
5
FN6682.3
December 6, 2011

5 Page
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Information Total 29 Pages
Download[ ISL12023.PDF Datasheet ]

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