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PDF ISL6615 Data sheet ( Hoja de datos )
| Número de pieza | ISL6615 | |
| Descripción | High-Frequency 6A Sink Synchronous MOSFET Drivers | |
| Fabricantes | Intersil | |
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Data Sheet
April 24, 2008
ISL6615
FN6481.0
High-Frequency 6A Sink Synchronous
MOSFET Drivers with Protection Features
The ISL6615 is a high-speed MOSFET driver optimized to
drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. This driver,
combined with an Intersil Digital or Analog multiphase PWM
controller, forms a complete high frequency and high
efficiency voltage regulator.
The ISL6615 drives both upper and lower gates over a range
of 4.5V to 13.2V. This drive-voltage provides the flexibility
necessary to optimize applications involving trade-offs
between gate charge and conduction losses.
The ISL6615 features 6A typical sink current for the low-side
gate driver, enhancing the lower MOSFET gate hold-down
capability during PHASE node rising edge, preventing power
loss caused by the self turn-on of the lower MOSFET due to
the high dV/dt of the switching node.
An advanced adaptive zero shoot-through protection is
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the dead
time. The ISL6615 includes an overvoltage protection
feature operational before VCC exceeds its turn-on
threshold, at which the PHASE node is connected to the
gate of the low side MOSFET (LGATE). The output voltage
of the converter is then limited by the threshold of the low
side MOSFET, which provides some protection to the load if
the upper MOSFET(s) is shorted.
The ISL6615 also features an input that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevent negative transients
on the controlled output voltage when operation is
suspended. This feature eliminates the need for the Schottky
diode that may be utilized in a power system to protect the
load from negative output voltage damage.
Features
• Dual MOSFET Drives for Synchronous Rectified Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
- LGATE Detection
- Auto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 6A LGATE Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Support 3.3V PWM Input logic
• Tri-State PWM Input for Safe Output Stage Shutdown
• Tri-State PWM Input Hysteresis for Applications with
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper PAD for Better Heat
Spreading
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-Free (RoHS Compliant)
Applications
• Optimized for POL DC/DC Converters for IBA Systems
• Core Regulators for Intel® and AMD® Microprocessors
• High Current Low-Profile DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• Synchronous Rectification for Isolated Power Supplies
Related Literature
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QFN Packages”
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6615
Electrical Specifications
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Tri-State Propagation Delay (Note 4)
OUTPUT (Note 4)
tPDHU
tPDHL
tPDLU
tPDLL
tPDTS
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load, Adaptive
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
VPVCC = 12V, 3nF Load
- 10 - ns
- 10 - ns
- 10 - ns
- 10 - ns
- 10 - ns
Upper Drive Source Current
IU_SOURCE VPVCC = 12V, 3nF Load
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
Upper Drive Sink Current
IU_SINK VPVCC = 12V, 3nF Load
Upper Drive Sink Impedance
RU_SINK 150mA Sink Current
Lower Drive Source Current
IL_SOURCE VPVCC = 12V, 3nF Load
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
Lower Drive Sink Current
IL_SINK VPVCC = 12V, 3nF Load
Lower Drive Sink Impedance
RL_SINK 150mA Sink Current
NOTE:
4. Limits established by characterization and are not production tested.
- 2.5 -
-1-
-4-
- 0.8 -
-4-
- 0.7 -
-6-
- 0.45 -
A
Ω
A
Ω
A
Ω
A
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1 1 UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2 2 BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the “TIMING
DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.
- 3, 8 N/C No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
3 4 PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the “TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of
the controller.
4 5 GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5 6 LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6 7 VCC Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
7 9 PVCC This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
8 10 PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9 11 PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5 FN6481.0
April 24, 2008
5 Page 
ISL6615
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
E
-B-
H
0.25(0.010) M B M
123
-A-
D
SEATING PLANE
A
L
h x 45°
-C-
e A1
B
0.25(0.010) M C A M B S
α
0.10(0.004)
C
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerances per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.0532 0.0688 1.35
1.75
-
A1
0.0040 0.0098 0.10
0.25
-
B
0.013 0.020 0.33
0.51
9
C
0.0075 0.0098 0.19
0.25
-
D
0.1890 0.1968 4.80
5.00
3
E
0.1497 0.1574 3.80
4.00
4
e 0.050 BSC
1.27 BSC
-
H
0.2284 0.2440 5.80
6.20
-
h
0.0099 0.0196 0.25
0.50
5
L
0.016 0.050 0.40
1.27
6
N8
87
α 0° 8° 0° 8° -
Rev. 1 6/05
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
11 FN6481.0
April 24, 2008
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL6615.PDF ] | |
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