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PDF HIP2103 Data sheet ( Hoja de datos )
| Número de pieza | HIP2103 | |
| Descripción | Half Bridge Driver | |
| Fabricantes | Intersil | |
| Logotipo |  |
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60V, 1A/2A Peak, Half Bridge Driver with 4V UVLO
HIP2103, HIP2104
The HIP2103 and HIP2104 are half bridge drivers designed for
applications using DC motors, three-phase brushless DC
motors, or other similar loads.
Two inputs (HI and LI) are provided to independently control
the high side driver (HO) and the low side driver (LO).
Furthermore, the two inputs can be configured to
enable/disable the device, thus lowering the number of
connections to a microcontroller and lowering costs.
The very low IDD bias current in the Sleep Mode prevents
battery drain when the device is not in use, thus eliminating
the need for an external switch to disconnect the driver from
the battery.
A fail-safe mechanism is included to improve system reliability
and to minimize the possibility of catastrophic bridge failures
due to controller malfunction. Internal logic prevents both
outputs from turning on simultaneously when HI and LI are
both high simultaneously. Dead-time is still required on the
rising edge of the HI (or LI) input when the LI (or HI) input
transitions low.
Integrated pull-down resistors on all of the inputs (LI, HI, VDen
and VCen) reduces the need for external resistors. An active
low resistance pull-down on the LO output ensures that the low
side bridge FET remains off during the Sleep Mode or when
VDD is below the undervoltage lockout (UVLO) threshold.
The HIP2104 has a 12V linear regulator and a 3.3V linear
regulator with separate enable pins. The 12V regulator
provides internal bias for VDD and the 3.3V regulator provides
bias for an external microcontroller (and/or other low voltage
ICs), thus eliminating the need for discrete LDOs or DC/DC
converters.
The HIP2103 is available in a 3x3mm, 8 Ld TDFN package and
the HIP2104 is available in a 4x4mm, 12 Ld DFN package.
Features
• 60V maximum bootstrap supply voltage
• 3.3V and 12V LDOs with dedicated enable pins (HIP2104)
• 5µA sleep mode quiescent current
• 4V undervoltage lockout
• 3.3V or 5V CMOS compatible inputs with hysteresis
• Integrated bootstrap FET (replaces traditional boot strap diode)
Applications
• Half bridge, full bridge and BLDC motor drives
(see Figures 21, 22, 23)
• UPS and inverters
• Class-D amplifiers
• Any switch mode power circuit requiring a half bridge driver
Related Literature
• AN1896 “HIP2103, HIP2104 Evaluation Board User’s Guide”
• AN1899 “HIP2103, HIP2104 3-phase, Full or Half Bridge
Motor Drive User’s Guide”
VBAT
µController
VBAT
VCen
VCC
VDD
VDen
HB
HI HIP2104
LI
HO
HS
LO
VSS
EPAD
VBAT
DC
MOTOR
HB
VDD
VDD
HO
HI
HS HIP2103 LI
LO
VSS
EPAD
FIGURE 1. TYPICAL FULL BRIDGE APPLICATION
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
10
20 30 40
VBAT (VDC)
FIGURE 2. HIP2104 SHUTDOWN CURRENT vs VBAT
50
November 27, 2013
FN8276.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
HIP2103, HIP2104
Absolute Maximum Ratings (Note 5)
Supply Voltage VDD (HIP2103 only) . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Bridge Supply Voltage VBAT (HIP2104 Only) . . . . . . . . . . . . . . . -0.3V to 60V
High side Bias Voltage (VHB - VHS) (Note 10). . . . . . . . . . . . . . . -0.3V to 16V
Logic Inputs VCen, VDen (HIP2104 Only) . . . . . . . . . . - 0.3v to VBAT+ 0.3V
Logic Inputs LI, HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3v to VDD+ 0.3V
Output Voltage LO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to VDD + 0.3V
Output Voltage HO . . . . . . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to VHB+ 0.3V
Voltage on HS (Note 9, 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10V to 60V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VHS - 0.3V to 66V
Average Current in Boot Diode (Note 6). . . . . . . . . . . . . . . . . . . . . . . 100mA
Maximum Boot Cap Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µF
Average Output Current in HO and LO (Note 6) . . . . . . . . . . . . . . . . 200mA
ESD Ratings
Human Body Model Class 2 (Tested per JESD22-A114E) . . . . . . 2000V
Charged Device Model Class IV . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000V
Latch-Up (Tested per JESD-78B; Class 2, Level A) all pins. . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld DFN Package (Notes 7, 8). . . . . . . . . .
46
7
12 Ld TDFN Package (Notes 7, 8) . . . . . . .
44
7
Max Power Dissipation at +25°C in free air
8 Ld DFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3W
12 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2W
Max Power Dissipation at +25°C on copper plane
8 Ld DFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3W
12 Ld TDFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3W
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Maximum Operating Junction Temperature Range. . . . . . -40°C to +150°C
Nominal Over Temperature Shut-down . . . . . . . . . . . . . . . . . . . . . . .+155°C
Over Temperature Shut-down Range . . . . . . . . . . . . . . . +145°C to +165°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions (Note 5)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Supply Voltage, VBAT(HIP2104 only) (Note 11). . . . . . . . . . . . . 5.0V to 50V
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
High Side Bias Voltage (VHB - VHS) (Note 10) . . . . . . . . . . . . . . -0.3V to 14V
Voltage on HS, Continuous, VHS (Notes 9, 10) . . . . . . . . . . . . . .-10V to 50V
Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS - 0.3V to 60V
Logic Inputs VCen, VDen (HIP2104 only). . . . . . . . . . . . . . . . . . . .0V to VBAT
Output Voltage (LO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND to VDD
Output Voltage (HO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHS to VHB
Average Output Current in HO and LO (Note 6) . . . . . . . . . . . . 0 to 150mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. All voltages are referenced toVSS unless otherwise specified.
6. The average output current, when driving a power MOSFET or similar capacitive load, is the average of the rectified output current. The peak output
currents of this driver are self limiting by trans conductance or rDS(ON) and do not required any external components to minimize the peaks. If the
output is driving a non-capacitive load, such as an LED, the maximum output current must be limited by external means to less than the specified
recommended rectified average output current.
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
9. The the maximum value of VHS must be limited so that VHB does not exceed 60V.
10. The -10V limit for VHS has no time duration restrictions as far as the HS pin is concerned however, be aware that if the duration of the negative voltage
is significant with respect to the time constant to charge the boot capacitor (across HB and HS) the voltage on the boot capacitor can charge as high
as VDD - (-VHS) = (VDD +VHS) potentially violating the Voltage Rating for (VHB - VHS).
11. When VBAT < ~13V, the output of VDD will sag. The 5V minimum specified for VBAT is the minimum level for which the UVLO will not activate.
DC Electrical Specifications VDD = VHB = 12V (for HIP2103), VSS = VHS = 0V, VBAT = 18V (for HIP2104), LI = HI = 0V. No load on HO
and LO unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = +25°C
MIN TYP MAX
TJ = -40°C to +125°C
MIN
(Note 12)
MAX
(Note 12)
UNITS
LINEAR BIAS SUPPLIES (HIP2104 only)
VDD Output Voltage Over Rated
Line, Load, and Temperature
VDD12 Nominal VDD = 12V
-2.5 +2.1 +4.8
- 5%
+ 5%
%
VDD Rated Output Current
VDD Output Current Limit
(brick wall)
IDDR
IDD12
75
83 151 237
80
mA
245 mA
VDD Drop Output Voltage
(Figure 7)
VDdout Load = 75mA
0.06 0.7 V
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FN8276.0
November 27, 2013
5 Page 
HIP2103, HIP2104
Typical Performance Curves
14
12 NO LOAD
160Ω (75mA @ 12V)
10
8
6
4
2
0
20 18 16 14 12 10 8 6 4 2
FIGURE 7. VDD DROPOUT vs VBAT (HIP2104 ONLY)
0
4
3
44Ω (75mA @ 3.3V)
2
NO LOAD
1
0
65 4 3 2
VBAT (INPUT)
FIGURE 8. VCC DROPOUT vs VBAT (HIP2104 ONLY)
1
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
10 20 30
VBAT (VDC)
FIGURE 9. HIP2104 SHUTDOWN CURRENT
(VCEN = VDEN = 0, HS = VBAT)
40
275
270
265
260
255
250
245
240
235
50 10 20 30 40 50
VBAT (VDC)
FIGURE 10. HIP2104 QUIESCENT IBAT (VCEN = VDEN = LI = HI = 1)
900
800 IBAT, 20k
700
IBAT, 10kHz
600
500
400
300
200 0kHz, +25°C
100
0
0 10 20 30 40 50
VBAT (VDC)
FIGURE 11. HIP2104 VDD OPERATING CURRENT LIMIT
60
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4
3
2
1
0
0 25 50 75 100 125
ICC (mA)
FIGURE 12. HIP2104 VCC CURRENT LIMIT
150
FN8276.0
November 27, 2013
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet HIP2103.PDF ] | |
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