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PDF XR18910 Data sheet ( Hoja de datos )
| Número de pieza | XR18910 | |
| Descripción | 8:1 Sensor Interface Analog Front End | |
| Fabricantes | Exar | |
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XR18910
8:1 Sensor Interface Analog Front End
Description
The XR18910 is a unique sensor interface integrated circuit with an
onboard 8:1 multiplexer, offset correction Digital-to-Analog Converter
(DAC), instrumentation amplifier and voltage reference. The XR18910
is designed to integrate multiple bridge sensors with a Microcontroller
(MCU) or Field-Programmable Gate Array (FPGA).
The integrated offset correction DAC provides digital calibration of the
variable and in many cases substantial offset voltage generated by the
bridge sensors. The DAC is controlled by an I2C compatible 2-wire serial
interface. The serial interface also provides the user with easy controls
to the XR18910’s many functions such as input and gain selection.
A linear regulator (LDO) provides a regulated voltage to power the input
bridge sensors and is selectable, between 3V and 2.65V. The LDO
current can be sensed and a proportional voltage present at the output
of the IC for monitoring the LDO current.
The XR18910 offers 8 fixed gain settings (from 2V/V to 760V/V), each
with an error of only ±0.5%, that are selectable via the I2C interface.
It also offers less than 3mV maximum input offset voltage, 100pA
maximum input bias current, and 100pA maximum input offset current.
The XR18910 is designed to operate from 2.7V to 5V supplies, specified
over the industrial temperature range of -40°C to 85°C and is offered in
a space saving 3.5mm x 3.5mm QFN package. It consumes less than
559μA supply current and offers a sleep mode for added power savings.
The XR18910 is well suited for industrial and consumer applications
using bridge sensors.
FEATURES
■■ Integrated features for interfacing multiple
bridge sensors with an MCU or FPGA
8:1 differential MUX with I2C interface
Instrumentation amplifier
LDO
Offset correction DAC with I2C interface
(±560mV offset correction range)
■■ Eight selectable voltage gains from 2V/V to
760V/V with only ±0.5% gain error
■■ 3mV maximum input offset voltage
■■ 100pA maximum input bias current
■■ 559μA maximum supply current
■■ 2.7V to 5V analog supply voltage range
■■ 1.8V to 5V digital supply voltage range
■■ -40°C to 85°C temperature range
■■ 3.5mm x 3.5mm QFN-24 package
APPLICATIONS
■■ Bridge sensor interface
■■ Pressure and temperature sensors
■■ Strain gauge amplifier
■■ Industrial process controls
■■ Weigh scales
Typical Application
BRIDGE 8
BRIDGE 1
6.8μF
+
VCC
6.8μF
+
VDD
0.1μF
BRDG VCC
0.1μF
VDD
IN8+
LDO
0.1μF
IN8-
8:1
MUX
IN1+
IN1-
INA / OUT 10k
PGA
±560mV
OFFSET TRIM
10-BIT
DAC
PGA
I2C
CONTROL
VDD
4.7k
SDA
SCL
10nF
VDD
4.7k
ADC
µC
XR18910
AGND
DGND
Figure 1. Typical Application
REV1A
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
2468
Time (seconds)
10
Figure 2. 0.1Hz to 10Hz RTI Voltage Noise
1/19
1 page  
REV. 1.0.0
XR20M1280
I2C/SPI UART WITH 128-BYTE FIFO AND INTEGRATED LEVXERL1S8H9IF1T0ERS
Electrical Characteristics (Continued)
FIGURE 22. I2C-BUS TIMING DIAGRAM
Protocol
SCL
SDA
START
condition
(S)
Bit 7
MSB
(A7)
TSU;STA
TLOW THIGH
Bit 6
(A6)
1/FSCL
TF
TR
TBUF
Bit 0
LSB
(R/W)
Acknowledge
(A)
STOP
condition
(P)
TSP
THD;STA
FIGURE 23. WRITE TO OUTPUT
TSU;DAT
THD;DAT
TVD;DAT
Figure 3. I2C Bus Timing Diagram
TVD;ACK
TSU;STO
SDA
GPIOn
SLAVE
ADDRESS
W A GPIOLVL REG. A
DATA
A
TD1
REV1A
5/19
5 Page 
Typical Performance Characteristics (Continued)
TA = 25°C, VCC = 3.3V, VDD = 1.8V, RL = 10kΩ to 1.5V, G = 760, unless otherwise noted.
XR18910
2.5
G=2
2
Stop Time = 1% Settling
1.5
DUT Output
1
0.5 SDA
0
-0.5
0
Start Time = 50% Acknowledge
5 10 15
20
Time (µs)
Figure 16. Sleep to Wake Time (DUT Output)
4
3.5
3
2.5 SDA
2
1.5 LDO Output
1
0.5 Stop Time = 1% Settling
0
Start Time = 50% Acknowledge
-0.5
0 50 100 150 200 250
Time (µs)
Figure 18. LDO Enable to Disable Time
4
3.5
3
2.5 SDA
Stop Time = 1% Settling
2
1.5 DUT Output
1 Start Time = 50% Acknowledge
0.5
0
0 5 10 15 20
Time (µs)
Figure 17. Set-up Time - from G = 2 to G = 300
(DUT Output)
3.5
3
2.5 LDO Output
2
Stop Time = 1% Settling
1.5
1
0.5 SDA
0
-0.5
0
Start Time = 50% Acknowledge
10 20 30 40
Time (µs)
Figure 19. LDO Disable to Enable Time
50
REV1A
11/19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet XR18910.PDF ] | |
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