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PDF TMC22091 Data sheet ( Hoja de datos )
| Número de pieza | TMC22091 | |
| Descripción | Digital Video Encoders/Layering Engine | |
| Fabricantes | Exar | |
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TMC22091/TMC22191
Digital Video Encoders/Layering Engine
Features
• All-digital video encoding
• Internal digital oscillators, no crystals required
• Multiple input formats supported
– 24-bit and 15-bit GBR/RGB
– YCBCR422 or 444
– Color indexed
• 30 overlay colors (TMC22191)
• Fully programmable timing
• Supports input pixel rates of 10 to 15 Mpps
• 256 x 8 x 3 color look-up tables (bypassable on
TMC22191)
• 8-bit mask register
• 8-bit composite digital video input
• Hardware and 24-bit data keying
• Synchronizes with TMC22071 Genlocking Video
Digitizer
• 8:8:8 video reconstruction
• SMPTE 170M NTSC or CCIR Report 624 PAL
compatible
• Supports PAL-M and NTSC without pedestal
• Simultaneous S-VIDEO (Y/C) NTSC/PAL output
• 10-bit D/A conversion (three channels)
Logic Symbol
BYPASS and OL4:0 on TMC22191 only.
24
PD23-0
6
OL4-0
PDC
VHSYNC
VVSYNC
KEY
BYPASS
CVBS7-0
GHSYNC
GVSYNC
8
RESET
D7-0
A1-0
CS
R/W
8
2
TMC22x91
DIGITAL
VIDEO
ENCODER
CHROMA
LUNA
COMPOSITE
VREF
COMP
RREF
TDI
TMS
TCK
TDO
LDV
PXCK
27008A
• Controlled edge rates
• 3 power-down modes
• Built-in color bars and modulated ramp test signals
• JTAG (IEEE Std 1149.1-1990) test interface
• Single +5V power supply
• 84 lead PLCC package
• 100 lead MQFP package
Description
The TMC22x91 digital video encoders convert digital com-
puter image or graphics data (in RGB, YCBCR, or color
indexed format) or a CCIR-601 signal into a standard analog
baseband television (NTSC or PAL) signal with a modulated
color subcarrier.
Both composite (single lead) and S-VIDEO (separate
chroma and luma) formats are active simultaneously at the
three analog output pins, each of which generates a standard
video-level signal into doubly-terminated 75Ω load.
The TMC22x91 accepts digitized video from the companion
TMC22071 Genlocking Video Digitizer. Soft switching
between video sources is done under either hardware or
programmable data control.
The TMC22191 offers 4-layer keying capability, bypassable
CLUT, and 30 Overlay colors.
The TMC22x91 is fabricated in a submicron CMOS process
and packaged in an 84 Lead Plastic Leadless Chip Carrier, or
in a 100 Lead Metric Quad Flat Pack. Performance is guar-
anteed from 0°C to 70°C.
Rev. 1.1.0
1 page  
PRODUCT SPECIFICATION
TMC22091/TMC22191
Microprocessor Interface
The microprocessor interface employs a 13 line format. The
RESET pin sets all internal state machines to their initialized
conditions, disables the analog outputs, sets the internal
SRESET bit LOW (reset condition), and places the encoder
in a power-down mode. All register and CLUT data are
maintained in power-down mode. If the HRESET bit is set
HIGH, line 1 field 1 is started when RESET goes HIGH, and
SRESET is ignored. If HRESET is LOW, the encoder
remains idle after RESET goes HIGH until Control Register
bit SRESET is set HIGH, which initiates line 1 field 1.
Two address lines are provided and decoded for access to the
internal Control Registers and CLUT. Control Registers and
CLUT are accessed by loading a desired address through the
8-bit D7-0 port, followed by the desired data read or write for
that address. Both the CLUT and the Control Registers are
self-indexing, allowing continuous reads or writes to succes-
sive addresses.
JTAG Test Interface
The TMC22x91 includes a standard 4-line JTAG (IEEE Std
1149.1-1990) test interface port, providing access to all digi-
tal input/output data pins. This is provided to facilitate com-
ponent and board-level testing.
Test/Validation Mode
The TMC22x91 may be configured to produce standard
color bars or a 40 IRE modulated (or unmodulated) video
ramp, independent of any pixel or video data input. Color
bars are useful as an idle system output signal. The test sig-
nals may be used to verify proper operation of the analog
video signal chain.
TMC22090/TMC22190 Compatibility
The TMC22090 and TMC22190 are earlier versions of the
TMC22091 and TMC22191, respectively. They lack the fol-
lowing features of the newer versions:
1. Selectable Setup (to support NTSC EIA-J video output
for Japan)
2. PAL-M format (for South American applications)
3. Extended EH and SL intervals (to support pixel rates
above 15 Mpps)
4. Individual D/A power-down (to reduce total dissipation
when some outputs are not required)
5. Luminance I/O processing (to reduce flicker in graphics
applications)
These features are controlled by registers 0E and 0F, and
enabled by setting Register OE bit 7 to ONE. If an applica-
tion of the TMC22x90 is programmed with this bit set to
ZERO (as recommended in the product documentation) then
the corresponding TMC22x91 will perform identically.
Though the earlier parts continue to be available, it is recom-
mended that the newer devices be used in new designs for
the additional flexibility. Older designs may be readily
converted to the newer versions to take advantage of the
added features and lower cost of the later technology.
5
5 Page 
PRODUCT SPECIFICATION
Table 2. Microprocessor Port Control
A1-0
00
R/W
0
Action
Write D7-0 into Control Register
pointer
00 1 Read Control Register pointer
on D7-0
01 0 Write D7-0 into CLUT Address
Pointer
01 1 Read CLUT Address Pointer on
D7-0
10 0 Write D7-0 to addressed Control
Register
10 1 Read addressed Control
Register on D7-0
11 0 Write D7-0 to addressed CLUT
location
11 1 Read addressed CLUT location
on D7-0
Table 3. Control Register Map
Reg Bit Name
Function
Global Control Register
00 7-5
Reserved
00 4 SRESET Software reset
00 3 PAL
Standard select, NTSC
or PAL
00 2 LUMDIS Luminance input disable
00 1 CHRDIS
Chrominance input
disable
00 0 HRESET Software reset disable
Format Control Register
01 7
Reserved
01 6 LCREN
Layering Control
Register enable
(TMC22191)
01 5 RAMPEN Modulated ramp test
01 4 CB
Color bar test
01 3-2 FORMAT
PD23-0 input format
select
01 1-0 INMODE
PD23-0 input mode
select
Interface Control Register
02 7 VITSEN
VITS lines enable
02 6 SHCY
Short-cycle test mode
02 5-4 TBASE
Time-base source select
02 3 SOUT
Sync output mode select
TMC22091/TMC22191
Table 3. Control Register Map (continued)
Reg Bit Name
Function
02 2 FBDIS
Frame buffer signals
disable
02 1 PDCDIR
PDC master, slave
select
02 0 FLDLK
Field lock select
Test Control Register
03 7
Reserved
03 6 LIMEN
Luminance limiter
enable
03 5 TESTEN Test enable
03 4 HOLDEN MSBs/LSBs hold select
03 3
TSTMSB
LSBs, MSBs in/out
select
03 2 LUMTST LUMA channel test
03 1 8FSUBR
8-field subcarrier reset
enable
03 0 CHRTST CHROMA channel test
Key Control Register
04 7
Reserved
04 6 HKEN
Hardware key enable
04 5 BUKEN
Burst key enable
04 4 SKEXT
Data key operation
select
04 3 DKDIS
Green/red/Y data key
disable
04 2 EKDIS
Blue/green/CB data key
disable
04 1 FKDIS
Red/blue/CR data key
disable
04 0 SKEN
Data key enable
Layering Control Register (TMC22191)
04 7
LAYMODE MSB of Layer
Assignments select
04 6 HKEN
Hardware key enable
04 5 BUKEN
Burst key enable
04 4 SKEXT
Data key operation
select
04 3-1 LAYMODE LSBs of Layer
Assignments select
04 0 SKEN
Data key enable
Key Value Registers
05 7-0 DKEY
Green/red/Y data key
value
06 7-0 EKEY
Blue/green/CB data key
value
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet TMC22091.PDF ] | |
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