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PDF TMC2491A Data sheet ( Hoja de datos )
| Número de pieza | TMC2491A | |
| Descripción | Multistandard Digital Video Encoder | |
| Fabricantes | Fairchild Semiconductor | |
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TMC2490A/TMC2491A
Multistandard Digital Video Encoder
www.fairchildsemi.com
Features
• All-digital video encoding
• Internal digital subcarrier synthesizer
• 8-bit parallel CCIR-601/CCIR-656/ANSI/SMPTE
125M input format
• CCIR-624/SMPTE-170M compliant output
• Switchable chrominance bandwidth
• Switchable pedestal with gain compensation
• Pre-programmed horizontal and vertical timing
• 13.5 Mpps pixel rate
• Master or slave (CCIR656) operation
• MPEG interface
• Internal interpolation filters simplify output
reconstruction filters
• 10-bit D/A converters for video reconstruction
• Supports NTSC and PAL standards
• Output encoding per Macrovision Copy Protection
(Revision 7.01) available (TMC2491A)
• Closed-caption waveform insertion
• Simultaneous S-Video (Y/C) output
• Controlled edge rates
• Single +5V power supply
• 44 lead PLCC package
• Parallel and serial control interface
Applications
• Set-top digital cable television receivers
• Set-top digital satellite television receivers
• Studio parallel CCIR-601 to analog conversion
Description
The TMC2490(1)A video encoder converts digital compo-
nent video (in 8-bit parallel CCIR-601/656 or ANSI/SMPTE
125M format) into a standard analog baseband television
(NTSC, NTSC-EIA, and all PAL standards) signal with a
modulated color subcarrier. Both composite (single lead) and
S-Video (separate chroma and luma) formats are active
simultaneously at all three analog outputs. Each video output
generates a standard video signal capable of driving a singly-
or doubly-terminated 75 Ohm load.
The TMC2491A is intended for those applications like DVD
or set-top boxes where Macrovision 7.01 compliance is
required. The TMC2490A is intended for all other non-
Macrovision encoder applications. A separate data sheet
supplement is available to Macrovision licensees.
The TMC2490(1)A is fabricated in a submicron CMOS
process and is packaged in a 44-lead PLCC. Performance is
guaranteed over the full 0°C to 70°C operating temperature
range.
Block Diagram
PD7-0
PIXEL DATA
DEMUX AND
SYNC
EXTRACT
PXCK
HSYNC
VSYNC, B/T
SELC
PDC/CBSEL
Y
LPF
INTERPOLATOR
4:2:2 TO 4:4:4
B-Y
R-Y
LPF
CHROMA
MODULATOR
INTER-
POLATION
FILTER
DIGITAL
SYNC AND
BLANK
GENERATOR
SUBCARRIER
SYNTHESIZER
INTER-
POLATION
FILTER
SERIAL/PARALLEL CONTROL
GLOBAL
CONTROL
10-BIT
D/A
10-BIT
D/A
10-BIT
D/A
REF
SERIAL
PARALLEL
SA1 SA0 SDA SCL D7-0
ADR R/W CS D7-0
SER RESET
CHROMA
LUMA
COMPOSITE
VREF
CBYP
RREF
65-2490(1)A-01
Rev. 1.0.1
1 page  
PRODUCT SPECIFICATION
Control Registers
The TMC2490(1)A is initialized and controlled by a set of
registers which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
TMC2490A/TMC2491A
serial interface port. The parallel port, D7-0, is governed by
pins CS, R/W, and ADR. The serial port is controlled by
SDA and SCL.
Table 1. Control Register Map
Reg Bit Mnemonic
Function
TMC2490(1)A Identification Registers (Read only)
00 7-0 PARTID2 Reads back 97h
01 7-0 PARTID1 Reads back 24h
02 7-0 PARTID0 Reads back 90h (91h)
03 7-0 REVID
Silicon revision #
Global Control Register
04 7 MASTER Master Mode
04 6 NGSEL NTSC Gain Select
04 5 YCDELAY Luma to chroma delay
04 4 RAMPEN Modulated ramp enable
04 3 YCDIS
LUMA, CHROMA disable
04 2 COMPDIS COMPOSITE disable
04 1-0 FORMAT Television standard select
Video Output Control Register
05 7 PALN
Select PAL-N Subcarrier
05 6 BURSTF Burst flag disable
05 5 CHRBW Chroma bandwidth select
05 4 SYNCDIS Sync pulse disable
05 3 BURDIS Color burst disable
05 2 LUMDIS Luminance disable
05 1 CHRDIS Chrominance disable
05 0 PEDEN Pedestal enable
Field ID Register
06 7-6 Reserved Program LOW
06 5-3 FIELD
Field ID (Read only)
06 2-0 Reserved Program LOW
Reserved Registers
07- 7-0 Reserved Program LOW
0D
Reg Bit Mnemonic
Function
General Purpose Port Register
0E 7 PORT7-6 General purpose Inputs
0E 6 PORT5-2 General purpose Outputs
0E 1 BURSTF Burst Flag Output
0E 0 CSYNC Composite Sync Output
General Control Register
0F 7 PED21
VBI Pedestal Enable
0F 5 VSEL
Vertical Sync Select
0F 4 CBSEL
CBSEL/PDC Pin Function
0F 3 VBIEN
VBI Pixel Data Enable
0F 1-0 HDSEL HSYNC Delay
Reserved Registers
10- 7-0 Reserved May be left unprogrammed
1F
Closed-Caption Insertion Registers
20 7-0 CCD1
First Byte of CC Data
21 7-0 CCD2
Second Byte of CC Data
22 7 CCON
Enable CC Data Packet
22 6 CCRTS Request To Send Data
22 5 CCPAR Auto Parity Generation
22 4 CCFLD CC Field Select
22 3-0 CCLINE CC Line Select
Notes:
1. For each register listed above, all bits not specified are
reserved and should be set to logic LOW to ensure proper
operation.
5
5 Page 
PRODUCT SPECIFICATION
TMC2490A/TMC2491A
General Purpose Port
The TMC2490(1)A provides a general purpose I/O port for
system utility functions. Input, output, and sync functions
are implemented. Register 0E is the General Purpose Regis-
ter.
Full functionality is provided when the encoder is in Serial
control mode (SER = LOW). Most of the functions are avail-
able in parallel interface mode (SER = HIGH).
General Purpose Input (serial mode only)
Bits 7 and 6 of Register 0E are general purpose inputs. When
the encoder is in serial control mode, data bits D7 and D6 are
mirrored to these register locations. When Register 0E is
read, the states of bits 7 and 6 reflect the TTL logic levels
present on D7 and D6, respectively, at the time of read com-
mand execution. Writing to these bits has no effect.
This function is not available when the encoder is in parallel
control mode.
General Purpose Output
Register 0E read/write bits 5-2 are connected to pins D5-2,
respectively, when the encoder is in serial control mode. The
output pins continually reflects the values most recently writ-
ten into register 0E (1 = HIGH, 0 = LOW). Note that these
pins are always driven outputs when the encoder is in serial
control mode.
When register 0E is read, these pins report the values previ-
ously stored in the corresponding register bits, i.e., it acts as
a read/write register. When the encoder is in parallel control
mode, this reading produces the output bit values on the cor-
responding data pins, just as in the serial control mode. How-
ever, the values are only present when reading register 0E.
The controller can command a continuous read on this regis-
ter to produce continuous outputs from these pins.
Burst Flag and Composite Sync (output/
read-only)
Register 0E bit 1 is associated with the encoder burst flag. It
is a 1 (HIGH) from just before the start of the color burst to
just after the end of the burst. It is a 0 (LOW) at all other
times.
Register 0E bit 0 outputs the encoder composite sync status.
It is a 0 (LOW) during horizontal and vertical sync tips. It is
a 1 (HIGH) at all other times.
These register bits may be read at any time over either the
serial or parallel control port. Since they are dynamic, their
states will change as appropriate during a parallel port read.
In fact, if the parallel control port is commanded to read reg-
ister 0E continually, the pins associated with these bits
behave as burst flag and composite sync timing outputs.
In serial control mode, these same data output pins (D1-0)
always act as a burst flag and composite sync TTL outputs,
the conditions of the serial control notwithstanding. The
states of the flags may be read over the serial port, but due to
the low frequency of the serial interface, it may be difficult to
get meaningful information.
Pixel Interface
The TMC2490(1)A interfaces with an 8-bit 13.5 Mpps (27
MHz) video datastream. It will automatically synchronize
with embedded Timing Reference Signals, per CCIR-656.
It also includes a master sync generator on-chip, which can
produce timing reference outputs.
CCIR-656 Mode
When operating in CCIR-656 Mode (MASTER = 0), the
TMC2490(1)A identifies the SAV and EAV 4-byte code-
words embedded in the video datastream to derive all timing.
Both SAV and EAV are required.
MASTER Mode
When in MASTER Mode (MASTER = 1), the Encoder
produces its own timing, and provides HSYNC, VSYNC (or
B/T), SELC, and PDC (or CBSEL) to the Pixel Data Source.
SELC Output
The SELC output toggles at 13.5 MHz (1/2 the pixel rate),
providing a phase reference for the multiplexed luma/chroma
CCIR-656 datastream. It is HIGH during the rising edge of
the clock intended to load chroma data. This is useful when
interfacing with a 16-bit data source, and can drive a Y/C
multiplexer.
CBSEL Output
The CBSEL output identifies the CB element of the CB-Y-
CR-Y CCIR-656 data sequence. It is HIGH during the rising
edge of the clock to load CB data. This will prevent uninten-
tionally swapping the CB and CR color components when
operating in MASTER mode and reading data from a
framestore.
PDC Output
The PDC output is a blanking signal, indicating when the
encoder expected to receive pixel data. When PDC is HIGH,
the incoming PD is encoded.
11
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| PDF Descargar | [ Datasheet TMC2491A.PDF ] | |
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