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PDF TMC2491A Data sheet ( Hoja de datos )
| Número de pieza | TMC2491A | |
| Descripción | Digital Video Encoder | |
| Fabricantes | Exar | |
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TMC2491A
Digital Video Encoder with
Macrovision™ Copy Protection
Features
• Macrovision™ Copy Protection Signal Processing
• All-Digital Video Encoding
• Internal Digital Synthesizer For Subcarrier Frequency
Generation
• 8-Bit Parallel CCIR-601 / SMPTE 170M Format
• Closed Caption Data Insertion
• Switchable Chrominance Bandwidth
• Switchable Pedestal With Gain Compensation
• Pre-Programmed Horizontal And Vertical Timing
• 13.5 Mpps Pixel Rate
• Synchronizes To Incoming Data Stream
• Master Timing Generator Mode
• Internal Interpolation Filters Simplify Output
Reconstruction Filters
• 9-Bit D/A Converters For Video Reconstruction
• Supports NTSC And PAL Standards
• Simultaneous S-Video (Y/C) Output
• Controlled Edge Rates
• Parallel And Serial Control Interface
• JTAG (IEEE Std 1149.1-1990) Test Interface
• Single +5V Power Supply
• 44 Lead PLCC Package
Applications
• Settop Digital Cable Television Receivers
• Settop Digital Satellite Television Receivers
Description
The TMC2491A video encoder converts digital component
video (in 8-bit parallel CCIR-601 or ANSI/SMPTE 125M
format) into a standard analog baseband television (NTSC,
NTSC-EIA, all PAL standards) signal with a modulated
color subcarrier. Both composite (single lead) and S-Video
(separate chroma and luma) formats are active simulta-
neously at the three analog outputs.
The TMC2491A includes all of the features of the
TMC2490A Digital Video Encoder, plus Macrovision™
copy protection signal processing. This datasheet is an
addendum to the TMC2490A specification.
Block Diagram
PD7-0
PIXEL DATA
DEMUX AND
SYNC
EXTRACT
LPF
INTERPOLATOR
4:2:2 TO 4:4:4
B-Y
R-Y
LPF
CHROMA
MODULATOR
INTER-
POLATION
FILTER
HSYNC
VSYNC
PXCK
DIGITAL SYNC
GENERATOR
SUBCARRIER
SYNTHESIZER
SYNC AND
Y
BLANK
INSERTER
SERIAL/PARALLEL CONTROL
GLOBAL
CONTROL
INTERPOLATION
FILTER
SERIAL
PARALLEL
SA1 SA0 SDA SCL D7-0
ADR R/W CS D7-0
SER RESET
9-BIT
D/A
CHROMA
9-BIT
D/A
LUMA
9-BIT
D/A
COMPOSITE
REF
VREF
CBYP
RREF
Rev. 1.0.0
1 page  
TMC2491A
PRODUCT SPECIFICATION
Table 2. Control Register Definitions — Changes/Additions to the TMC2490A
Reg Bit Mnemonic
Function
TMC2491A Identification Registers (Read only)
00 7-0 PARTID2 (Read only = 78h)
01 7-0 PARTID1 (Read only = 38h)
02 7-0 PARTID0 (Read only = 91h)
03 7-0
REVID
(Read only = revision #)
This specification applies to
TMC2491A circuits with REVID
>= to 02h. See revision B of
this document for circuits with
REVID - 01h.
Encoder Control Registers
04-0F 7-0 Controls Same as in TMC2490
Macrovision Control Registers
10 7-6
DBI7-6
Phase inversion enable bits.
Subcarrier phase inversion on
a line group-by-line group
basis is enabled whenever
DBI7-0 is not set equal to AAh.
10 5-0 N1 The 6-bit N1 value determines
the location of the 1st phase
inversion line of the 1st group
of inverse phase lines in the 1st
field. The position of this line
can be from 1 to 64 lines from
VSYNC. The default value for
N1 is 18 (22h) for NTSC and 48
(30h) for PAL.
11 7-6
11 5-0
DBI5-4
N2
Phase inversion enable bits
The 6-bit N2 value determines
the offset of the 2nd group of
inverse phase lines with
respect to the start of the 1st
group in the 1st field. The
position of this line can be from
1 to 64 lines from the start of
the 1st group. The default
value for N2 is 20 (14h) for
NTSC and 32 (20h) for PAL.
12 7-6
12 5-0
DBI3-2
N3
Phase inversion enable bits
The 6-bit N3 value determines
the location of the 1st phase
inversion line of the 1st group
of inverse phase lines in the
2nd field. The position of this
line can be from 1 to 64 lines
from VSYNC. The default
value for N3 is 18 (22h) for
NTSC and 48 (30h) for PAL.
13 7-6 DBI1-0 Phase inversion enable bits
Reg Bit Mnemonic
Function
13 5-0 N4 The 6-bit N4 value determines
the offset of the 2nd group of
inverse phase lines with
respect to the start of the 1st
group in the 2nd field. The
position of this line can be from
1 to 64 lines from the start of
the 1st group. The default
value for N2 is 20 (14h) for
NTSC and 32 (20h) for PAL.
14 7-6 N7 The number of phase inversion
lines per group varies by (2 +
N7). The 2-bit N7 value allows
the number of inverse phase
lines per group to vary from 2 to
5. The default value for N7 is 2
(0 in data mode).
14 5-3 N6 The number of phase inversion
groups per field varies by
(6+N6). The 3-bit N6 value
allows the number of groups
per field to vary from 6 to 13.
The default value for N6 is 4 for
NTSC and 3 for PAL.
14 2-0 N5 The spacing of groups varies
by (16+N5) for NTSC and
(12+N5) for PAL. The 3-bit N5
value allows the spacing of
groups to vary from 16 to 23 for
NTSC and from 12 to 19 for
PAL. The default value for N5
is 4.
15 7-6 reserved
15 5-3 N8A The A-pattern duration of p-
sync/AGC pulse pairs varies
by:
(24+(2xN8A)) for NTSC and
(16+(2xN8A)) for PAL. The
3-bit N8A value allows the
duration of p-sync/AGC pulse
pairs to vary from 24 to 38 for
NTSC and from 16 to 30 for
PAL. The default value for N8A
is 3 for NTSC and 4 for PAL.
15 2-0 N8B The B-pattern duration of
p-sync/AGC pulse pairs varies
by:
(24+(2xN8B)) for NTSC and
(16+(2xN8B)) for PAL. The 3-
bit N8B value allows the
duration of P-sync/AGC pulse
pairs to vary from 24 to 38 for
NTSC and from 16 to 30 for
PAL. The default value for N8B
is 0 for NTSC and PAL.
5
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