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PDF CS5519 Data sheet ( Hoja de datos )

Número de pieza CS5519
Descripción Enhanced Multi-touch Capacitive Touch Screen Controller
Fabricantes BCD 
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Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller
CS5519
General Description
The CS5519 is a low-cost high-resolution single chip
solution for APA capacitive touch screen. It is an
8-bit single cycle 8051 microcontroller with I2C
Interface. The chip includes 8-bit successive
approximation analog-to-digital converters with an
I2C interface and multiplexer-switcher circuits for
flexible measurement of analog signal from APA
panel. An accurate switched-capacitor integrator is
built-in and it can auto calibrate the pixel parameters
for a wide range of capacitance on the touch screen
(0.1pF to 4pF). On-chip capacitor can replace
external component. This touch screen controller
(TSC) with CMOS integration circuit provides an
ideal choice for APA touch panel. The CS5519 is
specified over the temperature range of -40°C to
95°C.
The CS5519 is available in QFN-7×7-56 and
QFN-8×8-68 packages.
Features
• Mutual Capacitive Touch Sensing
• Dual Power Supply: 2.8V to 3.6V Operation
Voltage; 1.6V to 2.0V Operation Voltage
• Up to 38/30 Drive Lines and 22/17 Sense Lines
• Dedicated Internal Two-wire Serial Control Bus
I2C and UART between CS5519 and Host
• Single-end Integrator with Programmable Gain
Control and Offset Control
• Multiplexed Analog Digitization with Two 8-bit
Resolution Odd/Even Scan SAR ADCs and Its
Dedicated 2X to 8X Accumulator XSRAM
Buffers
Features (Continued)
• Single Cycle 8051 CPU Core, Maximum Opera-
ting Clock up to 24MHz from IOSC (Zero Wait
State); 48MHz from IOSC(With Wait State)
4MHz to 48MHz Internal Oscillator (IOSC)
64K-byte Flash ROM
256-byte Internal SRAM and 12032-byte
XSRAM
Extra XSRAMs for AFE:
896×12-bit×2 XSRAM for 8-bit SAR ADC
896×8-bit XSRAM for 8-bit Parasitical
Capacitor Compensator
Two 16-bit Timers T0/T1 and One 16-bit ECT
Timer T2
One I2C Slave Controller and One I2C Master
Controller Shared with the Same Port
With Asynchronous I2C Slave Address
Detection Logic Design
4 General Purpose GPIO Pins
One External Interrupt Pin
One UART Data Transfer Output Pin
• ISP/IAP via I²C Port
• Operation Temperature Range: -40°C to 95°C
• Package Types: QFN-7×7-56 and QFN-8×8-68
• RoHS Compliance
• Operating Mode:
Mode
Power-down
Standard
Description
No scan with power-down mode
Higher scan rate when fingers are
on panel, IOSC can up to 4MHz
to 48MHz
Applications
• Mobile Phones
• Personal Digital Assistants
• Smart Hand-held or Gaming Devices
QFN-7×7-56
QFN-8×8-68
Figure 1. Package Types of CS5519
Apr. 2013 Rev. 1. 0
BCD Semiconductor Manufacturing Limited
1

1 page




CS5519 pdf
Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller
CS5519
Pin Description (Continued)
Pin Number
QFN-7×7
-56
QFN-8×8
-68
- 6 to 13
6 to 35
14 to 43
36 44
37 69
38 45
39 46
40 to 56 47 to 63
- 64 to 68
Pin
Name
D38 to
D31
D30 to
D1
P3.6/
RXD1
(open-
drain)
VSS
VDD18
VDD33
S1 to
S17
S18 to
S22
Pin
Type
Pin Function
O, A
O, A
I/O
Power
Power
Power
I, A
I, A
D38, D37, D36, D35, D34, D33, D32, D31
Driving line 38 to line 31
D30, D29, D28, D27, D26, D25, D24, D23, D22, D21,
D20, D19, D18, D17, D16, D15, D14, D13, D12, D11,
D10, D9, D8, D7, D6, D5, D4, D3, D2, D1
Driving line 30 to line 1
Port 3.6 GPIO
8051 P3.6 GPIO
This pin should be configured as open-drain output and
the input range can be 1.8V to 3.3V
RXD1
This pin also can be configured as RXD of UART 1
Ground Voltage. 0V
Internal Regulator Output. 1.6V to 2.0V
Typical decoupling capacitors of 0.1F and 10F should
be connected between VDD18 and VSS
Supply Voltage. 2.8V to 3.6V
A good decoupling capacitor between VDD33 and VSS is
critical for good performance
S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13,
S14, S15, S16, S17
Sensing line 1to line 17
S18, S19, S20, S21, S22
Sensing line 18 to line 22
Apr. 2013 Rev. 1. 0
BCD Semiconductor Manufacturing Limited
5

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CS5519 arduino
Data Sheet
Enhanced Multi-touch Capacitive Touch Screen Controller
CS5519
Electrical Characteristics (Continued)
DA/AC Characteristics for 8051 CPU Core, Digital GPIO pins, Digital Peripherals, and
IOSC
TA=–40°C to 95°C, VDD=2.8V to 3.6V, unless otherwise noted.
Parameter
Symbol
Min Typ Max
Power Supply Current
Normal Mode Supply Current
Using IOSC up to 48MHz
Normal Mode Supply Current
Using IOSC=4MHz
PMM Mode Supply Current Using
IOSC up to 48MHz
PMM Mode Supply Current Using
IOSC=4MHz
Idle Mode Supply Current Using
IOSC up to 48MHz
Stop Mode Supply Current Using
IOSC Keeps Low
Digital GPIO Characteristics
IDD, normal IOSC1
IDD, normal IOSC2
IDD, PMM IOSC1
IDD, PMM IOSC2
IDD, idle IOSC1
IDD, stop
25
2.9
6
1.5
3
3
Input High Voltage
VIH 2
3.6
Input Low Voltage
VIL -0.3
0.8
Output High Voltage
VOH 2.4
Output Low Voltage
VOL
0.4
High Level Output Current
@VOH(min)
IOH(2mA)
IOH(4mA)
3.0 7.87 12.9
7.7 15.6 25.8
Low Level Output Current
@VOL(max)
IOL(2mA)
IOL(4mA)
3.4 5.4 7.4
6.7 10.7 14.7
Input Pull Up Resistance
RPU 34
74
Input Pull Down Resistance
RPD 29
86
Input Low to High Level, RSTN
VIH, RSTN
0.85
0.93
Input High to Low Level, RSTN
VIL, RSTN
0.63
0.71
Output Rise Time
tRISE
5
Output Fall Time
tFALL
5
Internal 3.3V-to-1.8V LDO from AFE
Internal 1.8V Regulator Output
VDD18, 15mA
1.6 1.8 2.0
Power On/Off Reset Level
VDD18, Reset
80 85 90
Note 2: Does not include load current and tested under NOP loop and all peripheral disabled.
Note 3: For Digital I/O only.
Note 4: For RSTN pin only.
Note 5: Supply to internal digital and analog circuit only.
Note 6: This is measured as the percentage of steady state value of VDD18.
Note 7: This is measured with 20pF load and 20% to 80% output level.
Unit
mA
mA
mA
mA
mA
A
V
V
V
V
mA
mA
mA
mA
k
k
V
V
ns
ns
V
%
Note
2
2
2
2
2
2
3
3
3
3
3
3
4
4
7
7
5
6
Apr. 2013 Rev. 1. 0
BCD Semiconductor Manufacturing Limited
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