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PDF CS5508 Data sheet ( Hoja de datos )
| Número de pieza | CS5508 | |
| Descripción | 16-Bit and 20-Bit A/D Converters | |
| Fabricantes | Crystal | |
| Logotipo |  |
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CS5505/6/7/8
Very Low Power, 16-Bit and 20-Bit A/D Converters
Features
l Very Low Power Consumption
- Single supply +5 V operation: 1.7 mW
- Dual supply ±5 V operation: 3.2 mW
l Offers superior performance to VFCs and
multi-slope integrating ADCs
l Differential Inputs
- Single Channel (CS5507/8) and Four-Channel
(CS5505/6) pseudo-differential versions
l Either 5 V or 3.3 V Digital Interface
l Linearity Error:
- ±0.0015% FS (16-bit CS5505/7)
- ±0.0007% FS (20-bit CS5506/8)
l Output update rates up to 100/second
l Flexible Serial Port
l Pin-Selectable Unipolar/Bipolar Ranges
Description
The CS5505/6/7/8 are a family of low power CMOS A/D
converters which are ideal for measuring low-frequency
signals representing physical, chemical, and biological
processes.
The CS5507/8 have single-channel differential analog
and reference inputs while the CS5505/6 have four
pseudo-differential analog input channels. The
CS5505/7 have a 16-bit output word. The CS5506/8
have a 20-bit output word.The CS5505/6/7/8 sample
upon command up to 100 output updates per second.
The on-chip digital filter offers superior line rejection at
50 and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Hz.).
The CS5505/6/7/8 include on-chip self-calibration cir-
cuitry which can be initiated at any time or temperature
to ensure minimum offset and full-scale errors.
The CS5505/6/7/8 serial port offers two general-purpose
modes for the direct interface to shift registers or syn-
chronous serial ports of industry-standard
microcontrollers.
ORDERING INFORMATION
See page 30.
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Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
MAR ‘95
DS59F4
1
1 page  
CS5505/6/7/8
5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+VD+ = 5V ± 10%; VA-= -5V ± 10%;
DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter
Symbol Min Typ Max Units
High-Level Input Voltage:
XIN
M/SLP
All Pins Except XIN and M/SLP
VIH
VIH
VIH
3.5
0.9VD+
2.0
-
-
-
-V
-V
-V
Low-Level Input Voltage:
XIN
M/SLP
All Pins Except XIN and M/SLP
VIL
VIL
VIL
-
-
-
- 1.5 V
- 0.1VD+ V
- 0.8 V
M/SLP SLEEP Active Threshold
(Note 8) VSLP 0.45VD+ 0.5VD+ 0.55VD+ V
High-Level Output Voltage
(Note 9) VOH (VD+)-1.0
-
-V
Low Level Output Voltage
Input Leakage Current
Iout = 1.6 mA
VOL
Iin
-
-
- 0.4 V
1 10 µA
3-State Leakage Current
IOZ -
- ±10 µA
Digital Output Pin Capacitance
Cout
-
9
- pF
Notes:
8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP
pin enters the SLEEP active threshold range the device will enter the power down condition. Returning
to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse
of the wake-up period.
9. Iout = -100 µA. This guarantees the ability to drive one TTL load. (VOH = 2.4V @ Iout = -40 µA).
3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2)
Parameter
Symbol Min Typ Max Units
High-Level Input Voltage:
XIN
M/SLP
All Pins Except XIN and M/SLP
VIH
VIH
VIH
0.7VD+
0.9VD+
0.6VD+
-
-
-
-V
-V
-V
Low-Level Input Voltage:
XIN
M/SLP
All Pins Except XIN and M/SLP
VIL
VIL
VIL
-
-
-
- 0.3VD+ V
- 0.1VD+ V
- 0.16VD+ V
M/SLP SLEEP Active Threshold
(Note 8) VSLP 0.43VD+ 0.45VD+ 0.47VD+ V
High-Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Iout = -400 µA
Iout = 400 µA
VOH
VOL
Iin
(VD+)-0.3
-
-
-
-
1
-V
0.3 V
10 µA
3-State Leakage Current
IOZ -
- ±10 µA
Digital Output Pin Capacitance
Cout
-
9
- pF
DS59F4
5
5 Page 
CS5505/6/7/8
XIN
XIN/2
CONV
CS
STATE Standby
DRDY
SCLK(o) Hi-Z
Conversion
SDATA(o) Hi-Z
tcsd1
Standby
tph1
tcd1
MSB
tdd1
MSB-1
tpl1
Conversion
tfd2
LSB+1
LSB
Hi-Z
Hi-Z
STATE (CONV held high) Conversion1
Conversion2
Figure 3. Timing Relationships; SSC Mode (Not to Scale)
DRDY
CS
SDATA(o) Hi-Z
t csd2
SCLK(i)
MSB
tdd2
MSB-1
MSB-2
tfd3
DRDY
CS
SDATA(o) Hi-Z
SCLK(i)
t csd2
MSB
tdd2
MSB-1
LSB+2
t ph2
LSB+1
LSB
t pl2
Figure 4. Timing Relationships; SEC Mode (Not to Scale)
t fd4
DS59F4
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5508.PDF ] | |
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