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PDF CS5509 Data sheet ( Hoja de datos )
| Número de pieza | CS5509 | |
| Descripción | 16-Bit A/D Converter | |
| Fabricantes | Crystal | |
| Logotipo |  |
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CS5509
Single Supply, 16-Bit A/D Converter
Features
l Delta-Sigma A/D Converter
- 16-bit No Missing Codes
- Linearity Error: ±0.0015%FS
l Differential Input
- Pin Selectable Unipolar/Bipolar Ranges
- Common Mode Rejection
105 dB @ dc
120 dB @ 50, 60 Hz
l Either 5 V or 3.3 V Digital Interface
l On-chip Self-Calibration Circuitry
l Output Update Rates up to 200/second
l Ultra Low Power: 1.7 mW
Description
The CS5509 is a single supply, 16-bit, serial-output
CMOS A/D converter. The CS5509 uses charge-bal-
anced (delta-sigma) techniques to provide a low cost,
high resolution measurement at output word rates up to
200 samples per second.
The on-chip digital filter offers superior line rejection at
50 Hz and 60 Hz when the device is operated from a
32.768 kHz clock (output word rate = 20 Hz.).
The CS5509 has on-chip self-calibration circuitry which
can be initiated at any time or temperature to ensure
minimum offset and full-scale errors.
Low power, high resolution and small package size
make the CS5509 an ideal solution for loop-powered
transmitters, panel meters, weigh scales and battery
powered instruments.
ORDERING INFORMATION
CS5509-AP -40° to +85° C 16-pin Plastic DIP
CS5509-AS -40° to +85° C 16-pin SOIC
I
VREF+
9
VREF-
10
7
AIN+
8
AIN-
Differential
4th-Order
Delta-Sigma
Modulator
VA+ DGND VD+
11 12 13
Digital
Filter
Serial
Interface
Logic
1
CS
14 SCLK
15
SDATA
16
DRDY
Calibration SRAM
Calibration µC
OSC
2
CONV
45
XIN XOUT
3 CAL
6 BP/UP
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
Copyright © Cirrus Logic, Inc. 1997
(All Rights Reserved)
MAR ‘95
DS125F1
1
1 page  
CS5509
3.3V SWITCHING CHARACTERISTICS (TA = 25°C; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%;
Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2)
Parameter
Symbol
Master Clock Frequency Internal Oscillator:
External Clock:
XIN
fclk
Master Clock Duty Cycle
Rise Times:
Any Digital Input (Note 10) trise
Any Digital Output
Fall Times:
Any Digital Input (Note 10) tfall
Any Digital Output
Start-Up
Power-On Reset Period
(Note 11) tres
Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu
Wake-up Period
(Note 13) twup
Calibration
CONV Pulse Width (CAL=1)
CONV and CAL High to Start of Calibration
Start of Calibration to End of Calibration
(Note 14)
tccw
tscl
tcal
Conversion
CONV Pulse Width
tcpw
CONV High to Start of Conversion
tscn
Set Up Time
falling
BP/UP stable prior to DRDY
tbus
Hold Time
BP/UP stable after DRDY falls tbuh
Start of Conversion to End of Conversion
(Note 15) tcon
Min
30.0
30
40
-
-
-
-
-
-
-
100
-
-
100
-
82/fclk
0
-
Typ
32.768
-
-
-
50
-
20
Max
53.0
330
60
1.0
-
1.0
-
10
500
1800/fclk
-
-
-
--
- 2/fclk+200
3246/fclk
-
--
- 2/fclk+200
--
-
1624/fclk
-
-
Units
kHz
kHz
%
µs
ns
µs
ns
ms
ms
s
ns
ns
s
ns
ns
s
ns
s
DS125F1
5
5 Page 
output code. The only difference is that in bipo-
lar mode the on-chip microcontroller offsets the
computed output word by a code value of
8000H. This means that the bipolar measure-
ment range is not calibrated from full scale
positive to full scale negative. Instead it is cali-
brated from the bipolar zero scale point to full
scale positive. The slope factor is then extended
below bipolar zero to accommodate the negative
input signals. The converter can be used to con-
vert both unipolar and bipolar signals by
changing the BP/UP pin. Recalibration is not re-
quired when switching between unipolar and
bipolar modes.
At the end of the calibration cycle, the on-chip
microcontroller checks the logic state of the
CONV signal. If the CONV input is low the de-
vice will enter the standby mode where it waits
for further instruction. If the CONV signal is
high at the end of the calibration cycle, the con-
verter will enter the conversion state and
perform a conversion on the input channel. The
CAL signal can be returned low any time after
calibration is initiated. CONV can also be re-
turned low, but it should never be taken low and
then taken back high until the calibration period
has ended and the converter is in the standby
state. If CONV is taken low and then high
again with CAL high while the converter is cali-
brating, the device will interrupt the current
calibration cycle and start a new one. If CAL is
taken low and CONV is taken low and then high
during calibration, the calibration cycle will
continue as the conversion command is disre-
garded. The state of BP/UP is not important
during calibrations.
If an "end of calibration" signal is desired, pulse
the CAL signal high while leaving the CONV
signal high continuously. Once the calibration is
completed, a conversion will be performed. At
the end of the conversion, DRDY will fall to in-
dicate the first valid conversion after the
calibration has been completed.
CS5509
Conversion
The conversion state can be entered at the end of
the calibration cycle, or whenever the converter
is idle in the standby mode. If CONV is taken
high to initiate a calibration cycle ( CAL also
high), and remains high until the calibration cy-
cle is completed (CAL is taken low after CONV
transitions high), the converter will begin a con-
version upon completion of the calibration
period.
The BP/UP pin is not a latched input. The
BP/UP pin controls how the output word from
the digital filter is processed. In bipolar mode
the output word computed by the digital filter is
offset by 8000H (see Understanding Converter
Calibration). BP/UP can be changed after a con-
version is started as long as it is stable for 82
clock cycles of the conversion period prior to
DRDY falling. If one wishes to intermix meas-
urement of bipolar and unipolar signals on
various input signals, it is best to switch the
BP/UP pin immediately after DRDY falls and
leave BP/UP stable until DRDY falls again.
The digital filter in the CS5509 has a Finite Im-
pulse Response and is designed to settle to full
accuracy in one conversion time.
If CONV is left high, the CS5509 will perform
continuous conversions. The conversion time
will be 1622 clock cycles. If conversion is initi-
ated from the standby state, there may be up to
two XIN clock cycles of uncertainty as to when
conversion actually begins. This is because the
internal logic operates at one half the external
clock rate and the exact phase of the internal
clock may be 180° out of phase relative to the
XIN clock. When a new conversion is initiated
from the standby state, it will take up to two
XIN clock cycles to begin. Actual conversion
will use 1624 clock cycles before DRDY goes
low to indicate that the serial port has been up-
dated. See the Serial Interface Logic section of
DS125F1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS5509.PDF ] | |
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