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PDF CS5540 Data sheet ( Hoja de datos )
| Número de pieza | CS5540 | |
| Descripción | 24-Bit ADC | |
| Fabricantes | Crystal | |
| Logotipo |  |
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CS5540
Low-Power, Low-Voltage, 24 - Bit ∆Σ ADC
Features
l ∆Σ Analog-to-Digital Converter
- Linearity Error: 0.0015% FS
- RMS Noise: 4 µV
l Two Channel Differential MUX
l Buffered, Fully Differential Analog and
Voltage Reference Inputs
l Scalable VREF Input: 0.1 V to Analog Supply
l High Absolute Accuracy via Self-Calibration
l Fixed Digital Filter
- Single Conversion Settling at 6.7 SPS
- Simultaneous 50/60 Hz Rejection
l Simple Serial Interface
- SPITM and MicrowireTM Compatible
- Schmitt Trigger on Serial Clock (SCLK)
l Low Power
- Single +3.0 V Supply
- 330 µA Supply Current
- 10 µA in Sleep Mode
Description
The CS5540 is a low-power and low-voltage ∆Σ ana-
log-to-digital converter (ADC), which achieves highly
accurate conversions using a simple non-programmable
interface that is easy to understand and design-in. It is
optimized to convert analog signals in DC measurement
applications, such as temperature and pressure mea-
surement, and various portable devices where
low-power consumption is required.
To accommodate these applications, the ADC integrates
analog input and reference buffers for increased input
impedance and a two-channel multiplexer.
The CS5540 includes a digital filter, which achieves si-
multaneous rejection of 50/60 Hz signals and provides
single conversion settling at 6.7 SPS throughput. Abso-
lute accuracy is achieved via continuous internal
self-calibration. The device draws a nominal 330 µA.
Low-power, low-voltage operation, and a simple serial
interface make the CS5540 an ideal device for low-cost,
power-conscious DC measurement applications.
ORDERING INFORMATION
CS5540-AS -40 ºC - +85 ºC
16-Pin SSOP
VA+
CHS
AIN1+
AIN1-
AIN2+
AIN2-
Input
Mux
VREF+
VREF-
OSC1 OSC2
X1 X1
X1
Differential
4th Order
∆Σ
Modulator
X1
Clock
Generator
Digital
Filter
VA-
VD+
Serial
Interface
Calibration
Register
Output
Register
DGND
CS
SDO
SCLK
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2000
(All Rights Reserved)
JUN ‘01
DS503PP1
1
1 page  
CS5540
ANALOG CHARACTERISTICS (Continued)
Parameter
Analog Input
Common Mode + Signal on AIN+ or AIN-
Single Supply
Dual Supplies
CVF Current on AIN+, AIN-
Input Leakage for MUX when off
Common Mode Rejection
dc
50, 60Hz
Input Capacitance
Voltage Reference Input
Range
(VREF+) - (VREF-)
Min
(Note 6)
0.0
VA-
-
-
-
-
-
(Note 8) 0.1
Typ
-
-
12
10
120
120
8
2.5
CVF Current on VREF+ and VREF-
Common Mode Rejection
dc
50, 60 Hz
Input Capacitance
Dynamic Characteristics
Modulator Sampling Frequency
Filter Settling to 1/2 LSB (Full Scale Step)
6.7 SPS OWR
Power Supplies
DC Power Supply Currents
(Normal Mode)
IA+
ID+
Power Consumption
Normal Mode
Sleep Mode
Power Supply Rejection
dc Positive Supplies
dc Negative Supplies
(Note 7)
-
-
-
-
(Note 9)
-
-
20
120
120
12
MCLK/2
1/OWR
(Note 10)
-
-
-
-
-
-
225
25
750
30
80
80
Max
VA+
VA+
-
-
-
-
-
(VA+) -
(VA-)
-
-
-
-
-
-
280
36
1000
-
-
-
Units
V
V
nA
pA
dB
dB
pF
V
nA
dB
dB
pF
Hz
s
µA
µA
µW
µW
dB
dB
Notes: 6. See Section 2.1, “Analog Input”.
7. See Section 2.2, “Voltage Reference Input”.
8. Absolute voltages on VREF+ and VREF- must be less than or equal to the supply voltages.
9. The CS5540 includes a digital filter. The filter which achieves simultaneous rejection of 50/60 Hz
provides single conversion settling at a 6.7 SPS throughput.
10. All outputs unloaded. All inputs at CMOS levels.
DS503PP1
5
5 Page 
CS5540
2.2 Voltage Reference Input
The differential voltage between VREF+ and
VREF- sets the nominal full scale input span of the
converter. For a single-ended reference voltage, the
reference output is connected to the VREF+ pin of
the CS5540 and the ground reference is connected
to the VREF- pin. Note that the differential refer-
ence voltage can be from 0.1 V to ((VA+)- (VA-)).
The noise-free resolution of a single sample from
the ADC is directly proportional to the voltage ref-
erence as depicted in Figure 5.
Note:
When a lower reference voltage is used, the
resulting code widths are smaller. Since the
output codes exhibit more changing codes for
a fixed amount of noise, the converter
appears noisier.
2.2.1 Voltage Reference Input Model
Figure 6 illustrates the input models for the VREF
pins. It includes a coarse/fine charge buffer which
reduces the dynamic current demand of the exter-
nal reference. The reference’s buffer is designed to
accommodate rail-to-rail (common-mode plus sig-
nal) input voltages. Typical CVF (sampling) cur-
rent is about 16 nA (MCLK = 32.768 kHz).
in = CVosf
VREF
φ1 Fine
φ 2 Coarse
19
18
17
16
15
14
13
0 0.5 1 1.5 2 2.5 3
VREF (V)
Figure 5. Typical Noise-Free Resolution
vs. Voltage Reference
Noise-Free Res. = log2 (Bipolar Span/6.6*RMS Noise)
Vos≤ 25mV
C = 12 pF
f = 2*MCLK = 65.536 kHz
Figure 6. Input model for VREF+ and VREF- pins
DS503PP1
11
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet CS5540.PDF ] | |
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