|
|
PDF CY7C53120 Data sheet ( Hoja de datos )
| Número de pieza | CY7C53120 | |
| Descripción | Neuron Chip Network Processor | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY7C53120 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
CY7C53150, CY7C53120
Neuron Chip Network Processor
Features
■ Three 8-bit pipelined processors for concurrent processing of
application code and network traffic
■ 11-pin I/O port programmable in 34 modes for fast application
program development
■ Two 16-bit timer/counters for measuring and generating I/O
device waveforms
■ 5-pin communication port that supports direct connect and
network transceiver interfaces
■ Programmable pull-ups on I/O4–I/O7 and 20 mA sink current
on I/O0–I/O3
■ Unique 48-bit ID number in every device to facilitate network
installation and management
■ Low operating current; sleep mode operation for reduced
current consumption[1]
■ 0.35 m flash process technology
■ 5.0 V operation
■ On-chip LVD circuit to prevent nonvolatile memory corruption
during voltage drops
■ 2,048 bytes of SRAM for buffering network data, system, and
application data storage
■ 512 bytes (CY7C53150), 2048 bytes (CY7C53120E2), 4096
bytes (CY7C53120E4) of Flash memory with on-chip charge
pump for flexible storage of configuration data and application
code
■ Addresses up to 58 KB of external memory (CY7C53150)
■ 10 KB (CY7C53120E2), 12 KB (CY7C53120E4) of ROM
containing LonTalk network protocol firmware
■ Maximum input clock operation of 20 MHz (CY7C53150),
10 MHz (CY7C53120E2), 40 MHz (CY7C53120E4) over a
–40°C to 85°C[2] temperature range
■ 64-pin TQFP package (CY7C53150)
■ 32-pin SOIC or 44-pin TQFP package (CY7C53120)
Logic Block Diagram
Media Access
Control Processor
Network
Processor
Application
Processor
2 KB RAM
Flash
ROM
(CY7C53120)
Internal
Data Bus
(0:7)
Internal
Address Bus
(0:15)
Communications
Port
I/O Block
2 Timer/
Counters
CP4
CP0
I/O10
I/O0
Oscillator,
Clock, and
Control
CLK1
CLK2
SERVICE
RESET
External
Address/Data Bus
(CY7C53150)
Notes
1. Rare combinations of wake-up events occurring during the go to sleep sequence could produce unexpected sleep behavior.
2. Maximum Junction Temperature is 105 °C. TJunction = TAmbient + V•I•JA. 32-pin SOIC JA = 51 °C/W. 44-pin TQFP JA = 43 °C/W. 64-pin TQFP JA = 44 °C/W.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-10001 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 20, 2014
1 page  
CY7C53150, CY7C53120
Pin Configurations (continued)
Figure 2. 32-pin SOIC pinout and 44-pin QFP pinout
RESET
VDD
I/O4
I/O3
I/O2
I/O1
I/O0
SERVICE
VSS
Vpp
VDD
VDD
VSS
CLK2
CLK1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VDD
31 VSS
30 I/O5
29 I/O6
28 I/O7
27 I/O8
26 I/O9
25 VDD
24 I/O10
23 VSS
22 CP4
21 CP3
20 CP1
19 CP0
18 VDD
17 CP2
NC[4]
I/O6
I/O5
VSS
VDD
NC[4]
RESET
VDD
I/O4
I/O3
NC[4]
34
35
36
37
38
39
40
41
42
43
44
PIN 1
INDICATOR
CY7C53120Ex-yyAI
22
21
20
19
18
17
16
15
14
13
12
NC[4]
CP1
CP0
VDD
CP2
NC[4]
VSS
CLK1
CLK2
VSS
NC[4]
Document Number: 38-10001 Rev. *J
Page 5 of 19
5 Page 
CY7C53150, CY7C53120
Figure 4. Signal Loading for Timing Specifications Unless Otherwise Specified
TEST SIGNAL
CL
CL = 20 pF for E
CL = 30 pF for A0–A15, D0–D7, and R/W
CL = 50 pF for all other signals
Figure 5. Test Point Levels for E Pulse Width Measurements
PWEH
2.0 V
0.8 V
PWEL
2.0 V
Figure 6. Drive Levels and Test Point Levels for Timing Specifications Unless Otherwise Specified
DRIVE TO 2.4 V
DRIVE TO 0.4 V
2.0 V
0.8 V
A
B
2.0 V
0.8 V
A — Signal valid-to-signal valid specification (maximum or minimum)
B — Signal valid-to-signal invalid specification (maximum or minimum)
Figure 7. Test Point Levels for Driven-to-Three-State Time Measurements
VOH – 0.5 V
VOL + 0.5 V
VOH – Measured high output drive level
VOL – Measured low output drive level
Figure 8. Signal Loading for Driven-to-Three-State Time Measurements
TEST SIGNAL
CL = 30 pF
VDD/2
ILOAD = 1.4 mA
Document Number: 38-10001 Rev. *J
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY7C53120.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY7C53120 | Neuron Chip Network Processor | Cypress Semiconductor |
| CY7C53120L8 | 3.3V Neuron Chip Network Processor | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |