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PDF CY7C1061DV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1061DV18 | |
| Descripción | 16-Mbit (1M x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1061DV18
16-Mbit (1M × 16) Static RAM
16-Mbit (1 M × 16) Static RAM
Features
■ High Speed
❐ tAA = 15 ns
■ Low Active Power
❐ ICC = 150 mA at 67 MHz
■ Low complementary metal oxide semiconductor (CMOS)
Standby Power
❐ ISB2 = 25 mA
■ Operating voltages of 1.7 V to 2.2 V
■ 1.5 V data retention
■ Automatic power-down when deselected
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ Easy memory expansion with CE1 and CE2 features
■ Available in Pb-free 54-pin thin small outline package (TSOP)
Type II package
Functional Description
The CY7C1061DV18 is a high performance CMOS Static RAM
(SRAM) organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE1 LOW and CE2 HIGH)
while forcing the Write Enable (WE) input LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7),
is written into the location specified on the address pins (A0
through A19). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O8 through I/O15) is written into the location specified
on the address pins (A0 through A19).
To read from the device, enable the chip by taking CE1 LOW and
CE2 HIGH while forcing the Output Enable (OE) LOW and the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then
data from memory appears on I/O8 to I/O15. See the Truth Table
on page 11 for a complete description of Read and Write modes.
The input/output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE1 HIGH/CE2
LOW), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation (CE1
LOW, CE2 HIGH, and WE LOW).
The CY7C1061DV18 is available in a 54-pin TSOP II pinout.
For a complete list of related documentation, click here.
Logic Block Diagram
A0
A1
A2
AA34
A5
A6
AAA978
INPUT BUFFER
1M x 16
ARRAY
I/O0–I/O7
I/O8–I/O15
COLUMN
DECODER
BHE
WE
OE
BLE
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-08350 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 28, 2016
1 page  
CY7C1061DV18
Capacitance
Parameter [2]
Description
CIN
COUT
Input capacitance
I/O capacitance
Thermal Resistance
Parameter [2]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 1.8 V.
54-pin TSOP II Unit
6 pF
8 pF
Test Conditions
54-pin TSOP II Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
76.15
C/W
14.15
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [3]
OUTPUT
50
VTH = VDD/2
1.8V
R1 1667
Z0 = 50
30 pF* * Capacitive Load consists of all com-
OUTPUT
ponents of the test environment.
5 pF*
(a)
1.8V
ALL INPUT PULSES
90%
90%
INCLUDING
JIG AND
SCOPE (b)
GND
10%
10%
Rise time > 1 V/ns
(c)
Fall time:
> 1 V/ns
R2
1538
Notes
2. Tested initially and after any design or process changes that may affect these parameters.
3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (1.5 V). 150s (tpower) after reaching the minimum operating
VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 1.5 V) voltage.
Document Number: 001-08350 Rev. *L
Page 5 of 17
5 Page 
CY7C1061DV18
Truth Table
CE1 CE2 OE WE BLE BHE
I/O0–I/O7
HXXX X
X High Z
XLXX X
X High Z
LHLH L
L Data out
LHLH L
H Data out
LHLH H
L High Z
L HX L
L
L Data in
L HX L
L
H Data in
LHXL H
L High Z
LHHH X
X High Z
I/O8–I/O15
High Z
High Z
Data out
High Z
Data out
Data in
High Z
Data in
High Z
Mode
Power-down
Power-down
Read all bits
Read lower bits only
Read upper bits only
Write all bits
Write lower bits only
Write upper bits only
Selected, outputs disabled
Power
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Document Number: 001-08350 Rev. *L
Page 11 of 17
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY7C1061DV18.PDF ] | |
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