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Número de pieza | CY7C1046D | |
Descripción | 4-Mbit (1 M x 4) Static RAM | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CY7C1046D (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
No Preview Available ! CY7C1046D
4-Mbit (1 M × 4) Static RAM
4-Mbit (1 M × 4) Static RAM
Features
■ Pin- and function-compatible with CY7C1046B
■ High speed
❐ tAA = 10 ns
■ CMOS for optimum speed and power
■ Low active power
❐ ICC = 90 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 10 mA
■ Data retention at 2.0 V
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in lead-free 400-mil-wide 32-pin SOJ package
Functional Description
The CY7C1046D is a high-performance CMOS static RAM
organized as 1M words by 4 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and tri-state drivers. Writing to the device is
accomplished by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3)
is then written into the location specified on the address pins (A0
through A19).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The four input/output pins (I/O0 through I/O3) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CY7C1046D is available in a standard 400-mil-wide 32-pin
SOJ package with center power and ground (revolutionary)
pinout.
The CY7C1046D device is suitable for interfacing with
processors that have TTL I/P levels. It is not suitable for
processors that require CMOS I/P levels. Please see Electrical
Characteristics on page 4 for more details and suggested
alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
INPUT BUFFER
1M x 4
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05705 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 20, 2014
1 page CY7C1046D
Capacitance
Parameter [3]
Description
CIN
COUT
Input capacitance
I/O capacitance
Thermal Resistance
Parameter [3]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 5.0 V
Max Unit
8 pF
8 pF
Test Conditions
SOJ Package Unit
Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
53.44
C/W
38.25
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
OUTPUT
Z = 50
50
1.5 V
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
(a)
30 pF*
5V
3V
GND
Rise Time:1 V/ns
R1 481
ALL INPUT PULSES
90%
10%
90%VCC
10%VCC
(b) Fall Time: 1 V/ns
OUTPUT
5 pF
High Z Characteristics:
INCLUDING
JIG AND
SCOPE (c)
R2
255
Equivalent to: THÉVENIN EQUIVALENT
OUTPUT
167
1.73 V
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except high Z) are tested using the load conditions shown in (a). High Z characteristics are tested for all speeds using the test load shown in (c).
Document Number: 38-05705 Rev. *G
Page 5 of 16
5 Page CY7C1046D
Truth Table
CE OE
HX
LL
LX
LH
WE I/O0–I/O3
X High Z
H Data Out
L Data In
H High Z
Mode
Power-down
Read
Write
Selected, outputs disabled
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Document Number: 38-05705 Rev. *G
Page 11 of 16
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet CY7C1046D.PDF ] |
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