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PDF CY7C1020CV26 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1020CV26 | |
| Descripción | 512-Kbit (32 K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1020CV26
512-Kbit (32 K × 16) Static RAM
512-Kbit (32 K × 16) Static RAM
Features
■ Temperature range
❐ Automotive: –40 °C to 125 °C
■ High speed
❐ tAA = 15 ns
■ Optimized voltage range: 2.5 V to 2.7 V
■ Automatic power down when deselected
■ Independent control of upper and lower bits
■ CMOS for optimum speed and power
■ Package offered: 44-pin TSOP II
Functional Description
The CY7C1020CV26 is a high performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable (CE)
and write enable (WE) inputs LOW. If byte low enable (BLE) is
LOW, then data from I/O pins (I/O1 through I/O8), is written into
the location specified on the address pins (A0 through A14). If
byte high enable (BHE) is LOW, then data from I/O pins (I/O9
through I/O16) is written into the location specified on the address
pins (A0 through A14).
Reading from the device is accomplished by taking
chip enable (CE) and Output Enable (OE) LOW while forcing the
write enable (WE) HIGH. If byte low enable (BLE) is LOW, then
data from the memory location specified by the address pins
appears on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then
data from memory appears on I/O9 to I/O16. See the Truth Table
on page 11 for a complete description of read and write modes.
The input/output pins (I/O1 through I/O16) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CY7C1020CV26 is available in a standard 44-pin TSOP
Type II.
For a complete list of related documentation, click here.
Logic Block Diagram
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05406 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 14, 2015
1 page  
CY7C1020CV26
Capacitance
Parameter [3]
Description
CIN
COUT
Input capacitance
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 2.6 V
Max Unit
8 pF
8 pF
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [4]
2.6V
OUTPUT
30 pF
R 1830
R2
1976
2.5V
GND
ALL INPUT PULSES
90%
10%
(a)
Rise Time: 1 V/ns
(b)
90%
10%
Fall Time:1 V/ns
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of 1.3 V, input pulse levels of 0 to 2.5 V and transmission line loads as in (a)
of Figure 2.
Document Number: 38-05406 Rev. *G
Page 5 of 16
5 Page 
CY7C1020CV26
Truth Table
CE OE WE BLE BHE
I/O1–I/O8
H XX
X
X High Z
L LH
L
L Data Out
L H Data Out
H L High Z
L XL
L
L Data In
L H Data In
H L High Z
L HH
X
X High Z
L XX
H
H High Z
I/O9–I/O16
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
High Z
High Z
Mode
Power-Down
Read – All bits
Read – Lower bits only
Read – Upper bits only
Write – All bits
Write – Lower bits only
Write – Upper bits only
Selected, Outputs Disabled
Selected, Outputs Disabled
Power
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Document Number: 38-05406 Rev. *G
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY7C1020CV26.PDF ] | |
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