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PDF CY7C1010DV33 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1010DV33 | |
| Descripción | 2-Mbit (256 K x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C1010DV33
2-Mbit (256 K × 8) Static RAM
2-Mbit (256 K × 8) Static RAM
Features
■ Pin and function compatible with CY7C1010CV33
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 90 mA at 10 ns
■ Low CMOS standby power
❐ ISB2 = 10 mA
■ 2.0 V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 36-pin SOJ and 44-pin TSOP II packages
Functional Description
The CY7C1010DV33 is a high performance CMOS Static RAM
organized as 256 K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A17).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input and output pins (I/O0 through I/O7) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1010DV33 is available in 36-pin SOJ and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
For a complete list of related documentation, click here.
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
CE
WE
OE
INPUT BUFFER
256K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00062 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 19, 2014
1 page  
CY7C1010DV33
Capacitance
Parameter [3]
Description
CIN
COUT
Input capacitance
I/O capacitance
Thermal Resistance
Parameter [3]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 C, f = 1 MHz, VCC = 3.3 V
36-pin SOJ
8
8
44-pin TSOP II
8
8
Unit
pF
pF
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
36-pin SOJ 44-pin TSOP II Unit
59.17
50.66
C/W
32.63
17.77
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [4]
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
High-Z characteristics:
3.3 V
50
1.5 V
30 pF*
(a)
R 317
OUTPUT
(c)
5 pF
R2
351
3.0 V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 1 V/ns
(b) Fall Time: 1 V/ns
Notes
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High-Z characteristics are tested for all speeds using the test load shown
in Figure 3 (c).
Document Number: 001-00062 Rev. *F
Page 5 of 16
5 Page 
CY7C1010DV33
Ordering Information
Speed
(ns)
10
Ordering Code
CY7C1010DV33-10VXI
CY7C1010DV33-10ZSXI
Package
Diagram
Package Type
51-85090 36-pin (400-Mil) Molded SOJ (Pb-free)
51-85087 44-pin TSOP II (Pb-free)
Ordering Code Definitions
CY 7 C 1 01 0 D V33 - 10 XX X I
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = V or ZS
V = 36-pin (400-Mil) Molded SOJ
ZS = 44-pin TSOP II
Speed: 10 ns
V33 = Voltage range (3 V to 3.6 V)
Process Technology: D = C9, 90 nm Technology
Data Width: 0 = 8-bits
Density: 01 = 2-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Operating
Range
Industrial
Document Number: 001-00062 Rev. *F
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY7C1010DV33.PDF ] | |
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