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PDF CY7C107D Data sheet ( Hoja de datos )
| Número de pieza | CY7C107D | |
| Descripción | 1-Mbit (1 M x 1) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C107D
CY7C1007D
1-Mbit (1 M × 1) Static RAM
1-Mbit (1 M × 1) Static RAM
Features
■ Pin- and function-compatible with CY7C107B/CY7C1007B
■ High speed
❐ tAA = 10 ns
■ Low active power
❐ ICC = 80 mA @ 10 ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
❐ ISB2 = 3 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Transistor transistor logic (TTL) compatible inputs and outputs
■ CY7C107D available in Pb-free 28-pin 400-Mil wide Molded
SOJ package. CY7C1007D available in Pb-free 28-pin 300-Mil
wide Molded SOJ package
Functional Description
The CY7C107D [1] and CY7C1007D [1] are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy
memory expansion is provided by an active LOW Chip Enable
(CE) and tri-state drivers. These devices have an automatic
power-down feature that reduces power consumption by more
than 65% when deselected. The output pin (DOUT) is placed in a
high-impedance state when:
■ Deselected (CE HIGH)
■ When the write operation is active (CE and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the input pin (DIN) is written into the
memory location specified on the address pins (A0 through A19).
Read from the device by taking Chip Enable (CE) LOW while
while forcing Write Enable (WE) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins appears on the data output (DOUT) pin.
The CY7C107D and CY7C1007D devices are suitable for
interfacing with processors that have TTL I/P levels. It is not
suitable for processors that require CMOS I/P levels. Please see
Electrical Characteristics on page 4 for more details and
suggested alternatives.
For a complete list of related documentation, click here.
Logic Block Diagram
DIN
A0
A1
A2
A3
A4
A5
A6
A7
A8
CE
WE
INPUT BUFFER
1M x 1
ARRAY
DOUT
COLUMN DECODER
POWER
DOWN
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05469 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 24, 2014
1 page  
CY7C107D
CY7C1007D
Capacitance
Parameter [5]
Description
CIN: Addresses
CIN: Controls
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [5]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = 5.0 V
Max Unit
7 pF
10 pF
10 pF
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
300-Mil Wide
SOJ
400-Mil Wide
SOJ
Unit
59.16
58.76
C/W
40.84
40.54
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms [6]
OUTPUT
Z = 50
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
50
1.5V
(a)
30 pF*
3.0V
GND
ALL INPUT PULSES
90%
90%
10%
10%
Rise Time: 3 ns
(b) Fall Time: 3 ns
High-Z characteristics:
R1 480
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
(c)
R2
255
Notes
5. Tested initially and after any design or process changes that may affect these parameters.
6. AC characteristics (except High-Z) are tested using the load conditions shown in Figure 2 (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure 2 (c).
Document Number: 38-05469 Rev. *K
Page 5 of 15
5 Page 
CY7C107D
CY7C1007D
Package Diagrams
Figure 8. 28-pin SOJ (400 Mils) V28.4 (Molded SOJ V28) Package Outline, 51-85032
51-85032 *F
Document Number: 38-05469 Rev. *K
Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet CY7C107D.PDF ] | |
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