FM25C160B Datasheet PDF - Cypress Semiconductor
Part Number | FM25C160B | |
Description | 16-Kbit (2 K x 8) Serial (SPI) Automotive F-RAM | |
Manufacturers | Cypress Semiconductor | |
Logo | ||
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16-Kbit (2 K × 8) Serial (SPI) Automotive
F-RAM
16-Kbit (2 K × 8) Serial (SPI) Automotive F-RAM
Features
■ 16-Kbit ferroelectric random access memory (F-RAM) logically
organized as 2 K × 8
❐ High-endurance 10 trillion (1013) read/writes
❐ 121-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ Very fast serial peripheral interface (SPI)
❐ Up to 15 MHz frequency
❐ Direct hardware replacement for serial flash and EEPROM
❐ Supports SPI mode 0 (0,0) and mode 3 (1,1)
■ Sophisticated write protection scheme
❐ Hardware protection using the Write Protect (WP) pin
❐ Software protection using Write Disable instruction
❐ Software block protection for 1/4, 1/2, or entire array
■ Low power consumption
❐ 300 A active current at 1 MHz
❐ 10 A (typ) standby current at +85 C
■ Voltage operation: VDD = 4.5 V to 5.5 V
■ Automotive-E temperature: –40 C to +125 C
■ 8-pin small outline integrated circuit (SOIC) package
■ AEC Q100 Grade 1 compliant
■ Restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
Functional Description
The FM25C160B is a 16-Kbit nonvolatile memory employing an
advanced ferroelectric process. A ferroelectric random access
memory or F-RAM is nonvolatile and performs reads and writes
similar to a RAM. It provides reliable data retention for 121 years
while eliminating the complexities, overhead, and system level
reliability problems caused by serial flash, EEPROM, and other
nonvolatile memories.
Unlike serial flash and EEPROM, the FM25C160B performs
write operations at bus speed. No write delays are incurred. Data
is written to the memory array immediately after each byte is
successfully transferred to the device. The next bus cycle can
commence without the need for data polling. In addition, the
product offers substantial write endurance compared with other
nonvolatile memories. The FM25C160B is capable of supporting
1013 read/write cycles, or 10 million times more write cycles than
EEPROM.
These capabilities make the FM25C160B ideal for nonvolatile
memory applications requiring frequent or rapid writes.
Examples range from data collection, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of serial flash or EEPROM can cause data loss.
The FM25C160B provides substantial benefits to users of serial
EEPROM or flash as a hardware drop-in replacement. The
FM25C160B uses the high-speed SPI bus, which enhances the
high-speed write capability of F-RAM technology. The device
specifications are guaranteed over an automotive-e temperature
range of –40 C to +125 C.
For a complete list of related resources, click here.
WP
CS
HOLD
SCK
Instruction Decoder
Clock Generator
Control Logic
Write Protect
2Kx8
F-RAM Array
Instruction Register
Address Register
Counter
11
8
SI SO
Data I/O Register
3
Nonvolatile Status
Register
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-86150 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 14, 2015
|
|
FM25C160B
Data Transmission (SI/SO)
The SPI data bus consists of two lines, SI and SO, for serial data
communication. SI is also referred to as Master Out Slave In
(MOSI) and SO is referred to as Master In Slave Out (MISO). The
master issues instructions to the slave through the SI pin, while
the slave responds through the SO pin. Multiple slave devices
may share the SI and SO lines as described earlier.
The FM25C160B has two separate pins for SI and SO, which can
be connected with the master as shown in Figure 2.
For a microcontroller that has no dedicated SPI bus, a
general-purpose port may be used. To reduce hardware
resources on the controller, it is possible to connect the two data
pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.
Figure 3 shows such a configuration, which uses only three pins.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 16-Kbit serial F-RAM requires a 2-byte address for any read
or write operation. Because the address is only 11 bits, the first
five bits which are fed in are ignored by the device. Although
these three bits are ‘don’t care’, Cypress recommends that these
bits be set to 0s to enable seamless transition to higher memory
densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
FM25C160B uses the standard opcodes for memory accesses.
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin until the
next falling edge of CS, and the SO pin remains tristated.
Status Register
FM25C160B has an 8-bit Status Register. The bits in the Status
Register are used to configure the device. These bits are
described in Table 3 on page 7.
Figure 2. System Configuration with SPI port
SCK
MOSI
MISO
SPI
Microcontroller
CS1
HOLD1
WP1
CS2
HOLD2
WP2
SCK SI SO
FM25C160B
CS HOLD WP
SCK SI SO
FM25C160B
CS HOLD WP
Figure 3. System Configuration without SPI port
P1.0
P1.1
Microcontroller
SCK SI SO
FM25C160B
CS HOLD WP
P1.2
Document Number: 001-86150 Rev. *C
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