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PDF CY15B256J Data sheet ( Hoja de datos )
| Número de pieza | CY15B256J | |
| Descripción | 256-Kbit (32K x 8) Automotive Serial (I2C) F-RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY15B256J
256-Kbit (32K × 8) Automotive Serial (I2C)
F-RAM
256-Kbit (32K × 8) Automotive Serial (I2C) F-RAM
Features
■ 256-Kbit ferroelectric random access memory (F-RAM)
logically organized as 32K × 8
❐ High-endurance 100 trillion (1014) read/writes
❐ 151-year data retention (See the Data Retention and
Endurance table)
❐ NoDelay™ writes
❐ Advanced high-reliability ferroelectric process
■ Fast two-wire serial interface (I2C)
❐ Up to 3.4-MHz frequency[1]
❐ Direct hardware replacement for serial EEPROM
❐ Supports legacy timings for 100 kHz and 400 kHz
■ Device ID
❐ Manufacturer ID and Product ID
■ Low power consumption
❐ 175-A active current at 100 kHz
❐ 150-A standby current
❐ 8-A sleep mode current
■ Low-voltage operation: VDD = 2.0 V to 3.6 V
■ Automotive-A temperature: –40 C to +85 C
■ 8-pin small outline integrated circuit (SOIC) package
■ Restriction of hazardous substances (RoHS) compliant
Logic Block Diagram
Functional Description
The CY15B256J is a 256-Kbit nonvolatile memory employing an
advanced ferroelectric process. An F-RAM is nonvolatile and
performs reads and writes similar to a RAM. It provides reliable
data retention for 151 years while eliminating the complexities,
overhead, and system-level reliability problems caused by
EEPROM and other nonvolatile memories.
Unlike EEPROM, the CY15B256J performs write operations at
bus speed. No write delays are incurred. Data is written to the
memory array immediately after each byte is successfully
transferred to the device. The next bus cycle can commence
without the need for data polling. In addition, the product offers
substantial write endurance compared with other nonvolatile
memories. F-RAM also exhibits much lower power during writes
than EEPROM because write operations do not require an
internally elevated power supply voltage for write circuits. The
CY15B256J is capable of supporting 1014 read/write cycles, or
100 million times more write cycles than EEPROM.
These capabilities make the CY15B256J ideal for nonvolatile
memory applications, requiring frequent or rapid writes.
Examples range from data logging, where the number of write
cycles may be critical, to demanding industrial controls where the
long write time of EEPROM can cause data loss. The combi-
nation of features allows more frequent data writing with less
overhead for the system.
The CY15B256J provides substantial benefits to users of serial
EEPROM as a hardware drop-in replacement. The device incor-
porates a read-only Device ID that allows the host to determine
the manufacturer, product density, and product revision. The
device specifications are guaranteed over an Automotive-A
temperature range of –40 C to +85 C.
For a complete list of related documentation, click here.
Counter
Address
Latch
15
32 K x 8
F-RAM Array
SDA
SCL
WP
A0-A2
Serial to Parallel
Converter
Control Logic
8
Data Latch
8
8
Device ID and
Manufacturer ID
Note
1.
The CY15B256J does not
Refer to the DC Electrical
meet the NXP I2C specification in the
Characteristics table for more details.
Fast-mode
Plus
(Fm+,
1
MHz)
for
IOL
and
in
the
High
Speed
Mode
(Hs-mode,
3.4
MHz)
for
Vhys.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-90843 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 28, 2016
1 page  
CY15B256J
If the power supply drops below the specified VDD minimum
during operation, the system should issue a START condition
prior to performing another operation.
full pagewidth
SDA
Figure 3. START and STOP Conditions
SDA
SCL
S
START Condition
P
STOP Condition
SCL
handbook, full pagewidth
SDA
MSB
Figure 4. Data Transfer on the I2C Bus
Acknowledgement
signal from slave
P
Acknowledgement S
signal from receiver
SCL
S
1
START
condition
2
789
ACK
Byte complete
1
2 3 4-8
9
ACK
S
or
P
STOP or
START
condition
Data/Address Transfer
All data transfers (including addresses) take place while the SCL
signal is HIGH. Except under the three conditions described
above, the SDA signal should not change while SCL is HIGH.
Acknowledge / No-acknowledge
The acknowledge takes place after the 8th data bit has been
transferred in any transaction. During this state the transmitter
should release the SDA bus to allow the receiver to drive it. The
receiver drives the SDA signal LOW to acknowledge receipt of
the byte. If the receiver does not drive SDA LOW, the condition
is a no-acknowledge and the operation is aborted.
The receiver will fail to acknowledge for two distinct reasons, the
first being that a byte transfer fails. In this case, the
no-acknowledge ceases the current operation so that the part
can be addressed again. This allows the last byte to be
recovered in the event of a communication error.
The second and most common reason is that, the receiver does
not acknowledge to deliberately end an operation. For example,
during a read operation, the CY15B256J will continue to place
data on the bus as long as the receiver sends acknowledges
(and clocks). When a read operation is complete and no more
data is needed, the receiver must not acknowledge the last byte.
If the receiver acknowledges the last byte, this causes the
CY15B256J to attempt to drive the bus on the next clock while
the master is sending a new command such as STOP.
Figure 5. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
No Acknowledge
Acknowledge
SCL FROM
MASTER
S
START
Condition
1
2
89
Clock pulse for
acknowledgement
Document Number: 001-90843 Rev. *H
Page 5 of 19
5 Page 
CY15B256J
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS .........–1.0 V to +4.5 V
Input voltage* ......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
DC voltage applied to outputs
in HI-Z state ........................................ –0.5 V to VDD + 0.5 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VDD + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount lead soldering
temperature (3 seconds) ......................................... +260 C
Electrostatic discharge voltage
Human Body Model (JEDEC Std JESD22-A114-B) ................ 2 kV
Charged Device Model (JEDEC Std JESD22-C101-A) .......... 500 V
Latch-up current .................................................... > 140 mA
* Exception: The “VIN < VDD + 1.0 V” restriction does not apply
to the SCL and SDA inputs.
Operating Range
Range Ambient Temperature (TA)
VDD
Automotive-A
–40 C to +85 C
2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
Description
VDD Power supply
IDD Average VDD current
ISB VDD standby current
IZZ Sleep mode current
ILI Input leakage current
(Except WP and A2-A0)
Input leakage current
(for WP and A2-A0)
ILO Output leakage current
VIH Input HIGH voltage (SDL, SDA)
Test Conditions
SCL toggling
fSCL = 100 kHz
between
VDD – 0.2 V and VSS,
other inputs VSS or
fSCL = 1 MHz
fSCL = 3.4 MHz
VDD – 0.2 V.
SCL = SDA = VDD. All other inputs VSS
or VDD. Stop command issued.
SCL = SDA = VDD. All other inputs VSS
or VDD. Stop command issued.
VSS < VIN < VDD
VSS < VIN < VDD
VSS < VOUT < VDD
Min
2.0
–
–
–
–
–
–1
–1
–1
0.7 × VDD
Typ [2]
3.3
–
–
–
90
5
–
–
–
–
VIL
VOL[3]
Rin[4]
Vhys[5]
Input HIGH voltage (WP, A2-A0)
Input LOW voltage
Output LOW voltage
Input resistance (WP, A2-A0)
Hysteresis of Schmitt Trigger
inputs
IOL = 3 mA
IOL = 6 mA
For VIN = VIL(Max)
For VIN = VIH(Min)
fSCL = 100 kHz,
400 kHz, 1 MHz
0.7 × VDD
– 0.3
–
–
50
1
0.05 × VDD
–
–
–
–
–
–
–
fSCL = 3.4 MHz 0.06 × VDD
–
Notes
2.
3.
TTyhpeicCaYl v1a5lBu2e5s6aJredoaet s25no°tCm, VeDetDth=eVNDXD(PtyIp2)C.
Not 100% tested.
specification in the
Fast-mode
Plus
(Fm+,
1
MHz)
for
IOL
of
20
mA
at
a
VOL
of
0.4
V.
4.
5.
The
The
input pull-down circuit is strong
CY15B256J does not meet the
(50 k) when the input voltage is
NXP I2C specification in the High
below VIL and weak (1 M)
Speed Mode (Hs-mode, 3.4
when
MHz)
the
for
input voltage is above
Vhys of 0.1 × VDD.
VIH.
Max
3.6
175
400
1000
Unit
V
A
A
A
150 A
8 A
+1 A
+100
A
+1
VDD(max) +
0.3
VDD + 0.3
0.3 × VDD
0.4
0.6
–
–
–
A
V
V
V
V
V
k
M
V
–V
Document Number: 001-90843 Rev. *H
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY15B256J.PDF ] | |
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