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PDF CY7C1069G Data sheet ( Hoja de datos )
| Número de pieza | CY7C1069G | |
| Descripción | 16-Mbit (2M words x 8 bit) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1069G
CY7C1069GE
16-Mbit (2M words × 8 bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (2M words × 8 bit) Static RAM with Error-Correcting Code (ECC)
Features
■ High speed
❐ tAA = 10 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Low active and standby currents
❐ ICC = 90 mA typical at 100 MHz
❐ ISB2 = 20 mA typical
■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V
to 5.5 V
■ 1.0-V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Available in Pb-free 54-pin TSOP II, and 48-ball VFBGA
packages
Functional Description
The CY7C1069G and CY7C1069GE are dual chip enable
high-performance CMOS fast static RAM devices with
embedded ECC. The CY7C1069G device is available in
standard pin configurations. The CY7C1069GE device includes
a single bit error indication pin (ERR) that signals the host
processor in the case of an ECC error-detection and correction
event.
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location specified
on the address pins (A0 through A20).
To read from the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on the
I/O pins. See Truth Table – CY7C1069G/CY7C1069GE on page
14 for a complete description of Read and Write modes. The
input and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE1 HIGH or
CE2 LOW), the outputs are disabled (OE HIGH), or during a write
operation (CE1 LOW, CE2 HIGH, and WE LOW).
On CY7C1069GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High) [1].
All I/Os (I/O0 through I/O7) are placed in a high impedance state
when the device is deselected (CE1 HIGH or CE2 LOW), and
control signals are de-asserted (CE1 / CE2, OE, WE).
CY7C1069G and CY7C1069GE devices are available in a
54-pin TSOP II package with center power and ground
(revolutionary) pinout, and in a 48-ball VFBGA package.
For a complete list of related documentation, here.
Note
1. Automatic write back on error detection feature is not supported in this device.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-81539 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 14, 2016
1 page  
CY7C1069G
CY7C1069GE
Pin Configurations (continued)
Figure 3. 48-ball VFBGA pinout (Top View) – CY7C1069G [4]
1 2 34 56
NC OE A0 A1 A2 CE2 A
NC NC A3 A4 CE1 NC
B
I/O0 NC A5 A6 NC I/O4 C
VSS I/O1 A17 A7 I/O5 VCC
D
VCC I/O2 A18 A16 I/O6 VSS
E
I/O3 NC A14 A15 NC I/O7 F
NC NC A12 A13 WE NC
G
A19 A8 A9 A10 A11 A20
H
Figure 4. 48-ball VFBGA pinout (Top View) – CY7C1069GE [4, 5]
Note
4. NC pins are not connected on the die.
5. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81539 Rev. *I
Page 5 of 20
5 Page 
CY7C1069G
CY7C1069GE
Switching Waveforms
Figure 7. Read Cycle No. 1 of CY7C1069G (Address Transition Controlled) [25, 26]
tRC
ADDRESS
DATA I/O
tOHA
tAA
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 8. Read Cycle No. 2 of CY7C1069GE (Address Transition Controlled) [25, 26]
ADDRESS
tRC
DATA I/O
ERR
tOHA
tAA
PREVIOUS DATAOUT
VALID
tOHA
tAA
PREVIOUS ERR VALID
DATAOUT VALID
ERR VALID
Notes
25. The device is continuously selected, OE = VIL, CE = VIL.
26. WE is HIGH for read cycle.
Document Number: 001-81539 Rev. *I
Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet CY7C1069G.PDF ] | |
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