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PDF CY7C10612G Data sheet ( Hoja de datos )
| Número de pieza | CY7C10612G | |
| Descripción | 16-Mbit (1M x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C10612G
CY7C10612GE
16-Mbit (1M × 16) Static RAM
16-Mbit (1M × 16) Static RAM
Features
■ High speed
❐ tAA = 10 ns
■ Embedded error-correcting code (ECC) for single-bit error
correction
■ Low active power
❐ ICC = 90 mA typical
■ Low CMOS standby power
❐ ISB2 = 20 mA typical
■ Operating voltages of 3.3 ± 0.3 V
■ 1.0 V data retention
■ Transistor-transistor logic (TTL) compatible inputs and outputs
■ ERR pin to indicate 1-bit error detection and correction
■ Available in Pb-free 54-pin TSOP II package
Functional Description
The CY7C10612G and CY7C10612GE are high performance
CMOS fast static RAM devices with embedded ECC. These
devices are offered in single chip enable option. The
CY7C10612GE device includes an error indication pin that
signals an error-detection and correction event during a read
cycle.
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Truth Table on page 14 for a
complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
On the CY7C10612GE devices the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = high). See the Truth Table
on page 14 for a complete description of read and write modes.
The CY7C10612G and CY7C10612GE are available in a 54-pin
TSOP II package.
For a complete list of related documentation, click here.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
Description
-10 Unit
10 ns
110 mA
30 mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-88702 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 15, 2016
1 page  
Pin Configurations (continued)
Figure 2. 54-pin TSOP II pinout with ERR (Top View) [2, 3]
CY7C10612GE
CY7C10612G
CY7C10612GE
Note
2. NC pins are not connected on the die.
3. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-88702 Rev. *E
Page 5 of 19
5 Page 
CY7C10612G
CY7C10612GE
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23]
ADDRESS
CE
OE
BHE/
BLE
DATA I/O
VCC
SUPPLY
CURRENT
tRC
tACE
tDOE
tLZOE
tLZBEtDBE
HIGH IMPEDANCE
tLZCE
tPU
tPD
tHZCE
tHZOE
DATAOUT VALID
tHZBE
HIGH
IMPEDANCE
ISB
Notes
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE transition LOW.
Document Number: 001-88702 Rev. *E
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY7C10612G.PDF ] | |
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