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PDF CY621472E30 Data sheet ( Hoja de datos )
| Número de pieza | CY621472E30 | |
| Descripción | 4-Mbit (256 K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY621472E30 MoBL®
4-Mbit (256 K × 16) Static RAM
4-Mbit (256 K × 16) Static RAM
Features
■ Very high speed: 45 ns
■ Temperature range
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 2.20 V to 3.60 V
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A (Industrial)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE Features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 44-pin thin small outline package
(TSOP) II package
■ Byte power down feature
Functional Description
The CY621472E30 is a high performance CMOS static RAM
(SRAM) organized as 256K words by 16 bits. This device
features advanced circuit design to provide ultra low active
current. It is ideal for providing More Battery Life™ (MoBL) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption when addresses are not toggling.
Placing the device into standby mode reduces power
consumption by more than 99 percent when deselected (CE1
HIGH or CE2 LOW or both BLE and BHE are HIGH). The input
and output pins (I/O0 through I/O15) are placed in a high
impedance state when:
■ Deselected (CE1 HIGH or CE2 LOW)
■ Outputs are disabled (OE HIGH)
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Write operation is active (CE1 LOW and CE2 HIGH and WE
LOW)
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A17). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A17).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
11 for a complete description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
POWER DOWN
CIRCUIT
A10
A9
A8
A7
AA65
A4
A3
A2
A1
A0
DATA IN DRIVERS
256K x 16
RAM Array
CE
BHE
BLE
COLUMN DECODER
I/O0–I/O7
I/O8–I/O15
BHE
WE
CE1
CE2
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-67798 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 18, 2014
1 page  
CY621472E30 MoBL®
Capacitance
Parameter [7]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [7]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max Unit
10 pF
10 pF
Test Conditions
44-pin TSOP II
Package
Unit
Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit 77 C/W
board
13 C/W
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
Figure 2. AC Test Loads and Waveforms
ALL INPUT PULSES
R2
VCC
10%
GND
Rise Time = 1 V/ns
90%
90%
10%
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
V
Parameters
R1
R2
RTH
VTH
2.50 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
Unit
V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-67798 Rev. *F
Page 5 of 16
5 Page 
CY621472E30 MoBL®
Truth Table
CE1
H
X[33]
X[33]
L
L
CE2
X[33]
L
X[33]
H
H
WE
X
X
X
H
H
L HH
L HH
L HH
L HH
LHL
LHL
LHL
OE BHE BLE
I/Os
Mode
Power
X X X High Z
X X X High Z
Deselect/Power-down Standby (ISB)
Deselect/Power-down Standby (ISB)
X H H High Z
Deselect/Power-down Standby (ISB)
L L L Data out (I/O0–I/O15) Read
Active (ICC)
L H L Data out (I/O0–I/O7); Read
I/O8–I/O15 in High Z
Active (ICC)
L L H Data out (I/O8–I/O15); Read
I/O0–I/O7 in High Z
H L L High Z
Output disabled
H H L High Z
Output disabled
H L H High Z
Output disabled
X
L
L Data in (I/O0–I/O15)
Write
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
X
H
L Data in (I/O0–I/O7);
Write
I/O8–I/O15 in High Z
X L H Data in (I/O8–I/O15); Write
I/O0–I/O7 in High Z
Active (ICC)
Active (ICC)
Note
33.
The
pins
‘X’ (Don’t care) state
is not permitted.
for
the
chip
enables
(CE1
and
CE2)
in
the
truth
table
refer
to
the
logic
state
(either
HIGH
or
LOW).
Intermediate
voltage
levels
on
these
Document Number: 001-67798 Rev. *F
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY621472E30.PDF ] | |
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