CY62256EV18 Datasheet PDF - Cypress Semiconductor
Part Number | CY62256EV18 | |
Description | 256-Kbit (32 K x 8) Static RAM | |
Manufacturers | Cypress Semiconductor | |
Logo | ||
There is a preview and CY62256EV18 download ( pdf file ) link at the bottom of this page. Total 15 Pages |
Preview 1 page No Preview Available ! CY62256EV18 MoBL®
256-Kbit (32 K × 8) Static RAM
256-Kbit (32 K × 8) Static RAM
Features
■ Very high speed: 70 ns
■ Temperature ranges:
❐ Industrial: –40 °C to +85 °C
■ Wide voltage range: 1.65 V to 2.25 V
■ Pin compatible with CY62256N
■ Ultra low standby power
❐ Typical standby current: 1 µA
❐ Maximum standby current: 4 µA
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Offered in Pb-free 28-pin Narrow SOIC package
Functional Description
The CY62256EV18 is a high performance CMOS static RAM
module organized as 32 K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE HIGH). The eight input
and output pins (I/O0 through I/O7) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), or a write operation is in
progress (CE LOW and WE LOW).
To write to the device, take chip enable (CE) LOW and write
enable (WE) LOW. Data on the eight I/O pins is then written into
the location specified on the address pin (A0 through A14).
To read from the device, take chip enable (CE LOW) and output
enable (OE) LOW while forcing write enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
For a complete list of related documentation, click here.
Logic Block Diagram
A10
A9
A8
AAA765
AA43
A2
CE
WE
OE
INPUTBUFFER
32K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-69650 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 21, 2015
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CY62256EV18 MoBL®
Capacitance
Parameter [7]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [7]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max Unit
10 pF
10 pF
Test Conditions
Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit
board
28-pin SOIC
76.56
36.07
Unit
°C/W
°C/W
AC Test Loads and Waveforms
VCC
OUTPUT
R1
30 pF
Figure 2. AC Test Loads and Waveforms
ALL INPUT PULSES
R2
VCC
GND
10%
90%
90%
10%
Rise Time = 1 V/ns
Fall Time = 1 V/ns
INCLUDING
JIG AND
SCOPE
Equivalent to: THEVENIN EQUIVALENT
OUTPUT
RTH
VTH
Parameters
R1
R2
RTH
VTH
1.8 V
13500
10800
6000
0.8
Unit
V
Note
7. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 001-69650 Rev. *D
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Information | Total 15 Pages | |
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