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PDF CY62177ESL Data sheet ( Hoja de datos )
| Número de pieza | CY62177ESL | |
| Descripción | 32-Mbit (2 M x 16/4 M x 8) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62177ESL MoBL®
32-Mbit (2 M × 16/4 M × 8) Static RAM
32-Mbit (2 M × 16/4 M × 8) Static RAM
Features
■ Thin small outline package-I (TSOP-I) configurable as
2 M × 16 or as 4 M × 8 static RAM (SRAM)
■ High-speed up to 55 ns
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 3 µA
❐ Maximum standby current: 25 µA
■ Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■ Easy memory expansion with CE1, CE2, and OE Features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 48-ball TSOP-I package
Functional Description
The CY62177ESL is a high performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits. This
device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL®) in portable applications such as cellular telephones.
The device also has an automatic power-down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE1 HIGH or CE2 LOW or both
BHE and BLE are HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when: deselected
(CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE
LOW).
To write to the device, take Chip Enables (CE1 LOW and CE2
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0 through
A20). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written to the location specified on the
address pins (A0 through A20). To read from the device, take
Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O0 to I/O7. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O8
to I/O15. See the Truth Table on page 11 for a complete
description of read and write modes.
For a complete list of related documentation, click here.
Logic Block Diagram
A10
A9
A
A
8
7
A6
A5
A4
A3
A2
A
A
1
0
DATA IN DRIVERS
2 M × 16
RAM Array
COLUMN DECODER
Power-down
Circuit
BHE
BLE
I/O0–I/O7
I/O8–I/O15
BYTE
BHE
WE
OE
BLE
CE2
CE1
CE2
CE1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-64709 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 17, 2015
1 page  
CY62177ESL MoBL®
Capacitance
Parameter [11]
Description
CIN
COUT
Input capacitance
Output capacitance
Thermal Resistance
Parameter [11]
Description
JA Thermal resistance
(junction to ambient)
JC Thermal resistance
(junction to case)
Test Conditions
TA = 25 °C, f = 1 MHz, VCC = VCC(typ)
Max Unit
15 pF
15 pF
Test Conditions
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
TSOP I
55.91
9.39
Unit
C/W
C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
VCC
Output
30 pF
R1
R2
VCC
GND
10%
Rise Time = 1 V/ns
All Input Pulses
90%
90%
10%
Fall Time = 1 V/ns
Including
JIG and
scope
Equivalent to: THEVENIN EQUIVALENT
Output
RTH
V
Table 1. AC Test Loads
Parameter
R1
R2
RTH
VTH
2.5 V
16667
15385
8000
1.20
3.0 V
1103
1554
645
1.75
5.0 V
1800
990
639
1.77
Unit
V
Note
11. Tested initially and after any design or process changes that may effect these parameters.
Document Number: 001-64709 Rev. *E
Page 5 of 16
5 Page 
CY62177ESL MoBL®
Truth Table
CE1
H
X[31]
X[31]
L
L
CE2
X[31]
L
X[31]
H
H
WE
X
X
X
H
H
L HH
LHL
LHL
LHL
L HH
L HH
L HH
OE BHE BLE
Inputs Outputs
X X[31] X[31] High Z
X X[31] X[31] High Z
X H H High Z
L L L Data out (I/O0–I/O15)
L H L High Z (I/O8–I/O15);
Data out (I/O0–I/O7)
L L H Data out (I/O8–I/O15);
High Z (I/O0–I/O7)
X L L Data in (I/O0–I/O15)
X H L High Z (I/O8–I/O15);
Data in (I/O0–I/O7)
X L H Data in (I/O8–I/O15);
High Z (I/O0–I/O7)
H L H High Z
H H L High Z
H L L High Z
Mode
Deselect/Power-down
Deselect/Power-down
Deselect/Power-down
Read
Read
Read
Write
Write
Write
Output disabled
Output disabled
Output disabled
Power
Standby (ISB)
Standby (ISB)
Standby (ISB)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Active (ICC)
Note
31. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
Document Number: 001-64709 Rev. *E
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CY62177ESL.PDF ] | |
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