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PDF CY7C2665KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C2665KV18 | |
| Descripción | 144-Mbit QDR II+ SRAM Four-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C2663KV18/CY7C2665KV18
144-Mbit QDR® II+ SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency) with ODT
144-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 550-MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
■ Available in 2.5-clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ Static random access memory (SRAM) uses rising edges
only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-die termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ Quad data rate (QDR®) II+ operates with 2.5-cycle read latency
when DOFF is asserted high
■ Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted low
■ Available in × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
■ Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Selection Guide
Maximum operating frequency
Maximum operating current
Description
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2663KV18: 8M × 18
CY7C2665KV18: 4M × 36
Functional Description
The CY7C2663KV18, and CY7C2665KV18 are 1.8 V
synchronous pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with four 18-bit words
(CY7C2663KV18), or 36-bit words (CY7C2665KV18) that burst
sequentially into or out of the device. Because data is transferred
into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turn arounds”.
These devices have an ODT feature supported for D[x:0],
BWS[x:0], and K/K inputs, which helps eliminate external
termination resistors, reduce cost, reduce board area, and
simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
550 MHz 450 MHz Unit
550 450 MHz
× 18 1090
940 mA
× 36 1520
1290
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44141 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 1, 2016
1 page  
CY7C2663KV18/CY7C2665KV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
WPS
BWS0,
BWS1,
BWS2,
BWS3
Input- Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
synchronous CY7C2663KV18 D[17:0]
CY7C2665KV18 D[35:0]
Input- Write port select Active low. Sampled on the rising edge of the K clock. When asserted active, a
synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
Input- Byte write select (BWS) 0, 1, 2, and 3 Active low. Sampled on the rising edge of the K and K clocks
synchronous when write operations are active. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C2663KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C2665KV18 BWS0 controls D[8:0], BWS1 controls D[17:9],
BAWll Sth2ecoBnWtrsolspiDn[s26a:1r8e] asnadmBpWledS3ocnonthtreolssaDm[3e5:2e7]d. ge as the data. Deselecting a BWS ignores the
corresponding byte of data and it is not written into the device.
A Input- Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8M × 18 (4 arrays each of 2M × 18) for CY7C2663KV18 and 4M × 36 (4 arrays each of
1M × 36) for CY7C2665KV18. Therefore, only 21 address inputs are needed to access the entire memory
array of CY7C2663KV18 and 20 address inputs for CY7C2665KV18. These inputs are ignored when
the appropriate port is deselected.
Q[x:0]
RPS
Outputs- Data output signals. These pins drive out the requested data when the read operation is active. Valid
synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tri-stated.
CY7C2663KV18 Q[17:0]
CY7C2665KV18 Q[35:0]
Input- Read port select Active low. Sampled on the rising edge of positive input clock (K). When active, a
synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tri-stated following the next rising edge
of the K clock. Each read access consists of a burst of four sequential transfers.
QVLD
ODT [3]
Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
ODT input pin ODT input. This pin is used for ODT of the input signals. ODT range selection is made during power-up
initialization. A low on this pin selects a low range that follows RQ/3.33 for 175 < RQ < 350 (where
RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a high range that follows RQ/1.66 for
175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When left floating, a high range termination
value is selected by default.
K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K Input clock Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
CQ Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.
CQ Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Note
3. On-Die Termination (ODT) feature is supported for D[x:0], BWS[x:0], and K/K inputs.
Document Number: 001-44141 Rev. *P
Page 5 of 31
5 Page 
CY7C2663KV18/CY7C2665KV18
Write Cycle Descriptions
The write cycle description table for CY7C2665KV18 follows. [14, 15]
BWS0 BWS1 BWS2 BWS3 K
L L L L L–H
K Comments
– During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Notes
14. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
15.
Is based
cycle, as
on a write cycle that was initiated in accordance with the
long as the setup and hold requirements are achieved.
Truth
Table
on
page
9.
BWS0,
BWS1,
BWS2,
and
BWS3
can
be
altered
on
different
portions
of
a
write
Document Number: 001-44141 Rev. *P
Page 11 of 31
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C2665KV18.PDF ] | |
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