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What is CY7C1263KV18?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "36-Mbit QDR II+ SRAM Four-Word Burst Architecture".


CY7C1263KV18 Datasheet PDF - Cypress Semiconductor

Part Number CY7C1263KV18
Description 36-Mbit QDR II+ SRAM Four-Word Burst Architecture
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY7C1263KV18/CY7C1265KV18
36-Mbit QDR® II+ SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency)
36-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Separate independent read and write data ports
Supports concurrent transactions
550 MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
Available in 2.5 clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Single multiplexed address input bus latches address inputs
for read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with one cycle read latency
when DOFF is asserted LOW
Available in × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD [1]
Supports both 1.5 V and 1.8 V I/O supply
HSTL inputs and variable drive HSTL output buffers
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
JTAG 1149.1 compatible test access port
Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1263KV18 – 2M × 18
CY7C1265KV18 – 1M × 36
Functional Description
The CY7C1263KV18, and CY7C1265KV18 are 1.8 V
synchronous pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with four 18-bit words
(CY7C1263KV18), or 36-bit words (CY7C1265KV18) that burst
sequentially into or out of the device. Because data is transferred
into and out of the device on every rising edge of both input
clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Description
Maximum operating frequency
Maximum operating current
× 18
× 36
550 MHz
550
850
1210
500 MHz 450 MHz
500 450
790 Not Offered
Not Offered 1020
400 MHz
400
660
920
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57833 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 16, 2016

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CY7C1263KV18 equivalent
CY7C1263KV18/CY7C1265KV18
Pin Definitions
Pin Name
D[x:0]
WPS
BWS0,
BWS1,
BWS2,
BWS3
A
Q[x:0]
RPS
QVLD
K
K
CQ
CQ
ZQ
DOFF
TDO
TCK
I/O Pin Description
Input- Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
synchronous CY7C1263KV18 D[17:0]
CY7C1265KV18 D[35:0]
Input- Write port select active LOW. Sampled on the rising edge of the K clock. When asserted active, a
synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
Input- Byte write select 0, 1, 2, and 3 active LOW. Sampled on the rising edge of the K and K clocks when
synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1263KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1265KV18 BWS0 controls D[8:0], BWS1 controls D[17:9],
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select
ignores the corresponding byte of data and it is not written into the device.
Input- Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 2M × 18 (4 arrays each of 512K × 18) for CY7C1263KV18 and 1M × 36 (4 arrays each of
256K × 36) for CY7C1265KV18. Therefore, only 19 address inputs are needed to access the entire
memory array of CY7C1263KV18 and 18 address inputs for CY7C1265KV18. These inputs are ignored
when the appropriate port is deselected.
Outputs- Data output signals. These pins drive out the requested data when the read operation is active. Valid
synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tristated.
CY7C1263KV18 Q[17:0]
CY7C1265KV18 Q[35:0]
Input- Read port select active LOW. Sampled on the rising edge of positive input clock (K). When active, a
synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge of
the K clock. Each read access consists of a burst of four sequential transfers.
Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input clock
Input clock
Echo clock
Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
Negative input clock input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.
Echo clock Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Input
PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull-up through a 10 Kor less pull-up resistor. The device behaves in QDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with QDR I timing.
Output TDO pin for JTAG.
Input TCK pin for JTAG.
Document Number: 001-57833 Rev. *K
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Featured Datasheets

Part NumberDescriptionMFRS
CY7C1263KV18The function is 36-Mbit QDR II+ SRAM Four-Word Burst Architecture. Cypress SemiconductorCypress Semiconductor

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