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PDF CY7C1613KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1613KV18 | |
| Descripción | 144-Mbit QDR II SRAM Four-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1613KV18/CY7C1615KV18
144-Mbit QDR® II SRAM Four-Word
Burst Architecture
144-Mbit QDR® II SRAM Four-Word Burst Architecture
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ Quad data rate (QDR®) II operates with 1.5-cycle read latency
when DOFF is asserted high
■ Operates similar to a QDR I device with one-cycle read latency
when DOFF is asserted low
■ Available in × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ Variable drive high-speed transceiver logic (HSTL) output
buffers
■ JTAG 1149.1 compatible test access port (TAP)
■ Phase Locked Loop (PLL) for accurate data placement
Configuration
CY7C1613KV18 – 8 M × 18
CY7C1615KV18 – 4 M × 36
Functional Description
The CY7C1613KV18, and CY7C1615KV18 are 1.8-V
synchronous pipelined SRAMs, equipped with QDR® II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turn around”
the data bus that exists with common I/O devices. Each port can
be accessed through a common address bus. Addresses for
read and write addresses are latched on alternate rising edges
of the input (K) clock. Accesses to the QDR II read and write
ports are completely independent of one another. To maximize
data throughput, both read and write ports are equipped with
DDR interfaces. Each address location is associated with four
18-bit words (CY7C1613KV18), or 36-bit words
(CY7C1615KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
× 18
× 36
333 MHz
333
760
1010
300 MHz
300
710
950
250 MHz Unit
250 MHz
Not Offered mA
830
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44273 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 30, 2015
1 page  
CY7C1613KV18/CY7C1615KV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
WPS
BWS0,
BWS1,
BWS2,
BWS3
Input- Data input signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C1613KV18 D[17:0]
CY7C1615KV18 D[35:0]
Input- Write port select Active low. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
Input- Byte write select (BWS) 0, 1, 2, and 3 Active low. Sampled on the rising edge of the K and K clocks
Synchronous when write operations are active. Used to select which byte is written into the device during the current
portion of the write operations. Bytes not written remain unaltered.
CY7C1613KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1615KV18 BWS0 controls D[8:0], BWS1 controls D[17:9],
BAWll tShe2 cboyntetrowlsritDe[2s6e:l1e8c] tasnadreBWsaSm3pcleodntoronlsthDe[3s5a:2m7]e. edge as the data. Deselecting a BWS ignores the
corresponding byte of data and it is not written into the device.
A Input- Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8 M × 18 (4 arrays each of 2 M × 18) for CY7C1613KV18 and 4 M × 36 (4 arrays each of
1 M × 36) for CY7C1615KV18. Therefore, only 21 address inputs are needed to access the entire
memory array of CY7C1613KV18 and 20 address inputs for CY7C1615KV18. These inputs are ignored
when the appropriate port is deselected.
Q[x:0]
RPS
Outputs- Data output signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the C and C clocks during read operations, or K and K when in
single clock mode. On deselecting the read port, Q[x:0] are automatically tristated.
CY7C1613KV18 Q[17:0]
CY7C1615KV18 Q[35:0]
Input- Read port select Active low. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tri-stated following the next rising edge
of the C clock. Each read access consists of a burst of four sequential transfers.
C Input Clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 8 for further details.
C Input Clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 8 for further details.
K Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K Input Clock Negative input clock input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q[x:0] when in single clock mode.
CQ Echo Clock CQ referenced with respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the Switching Characteristics on page 24.
CQ Echo Clock CQ referenced with respect to C. This is a free-running clock and is synchronized to the input clock
for output data (C) of the QDR II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the Switching Characteristics on page 24.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Document Number: 001-44273 Rev. *K
Page 5 of 32
5 Page 
CY7C1613KV18/CY7C1615KV18
Write Cycle Descriptions
The write cycle description table for CY7C1615KV18 follows: [12, 13]
BWS0 BWS1 BWS2 BWS3 K
L L L L L–H
K Comments
– During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Notes
12. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
13.
Is based on a write
write cycle, as long
cycle that was initiated in accordance with the Truth
as the setup and hold requirements are achieved.
Table
on
page
9.
BWS0,
BWS1,
BWS2,
and
BWS3
can
be
altered
on
different
portions
of
a
Document Number: 001-44273 Rev. *K
Page 11 of 32
11 Page | ||
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