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What is CY7C1414KV18?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "36-Mbit QDR II SRAM Two-Word Burst Architecture".


CY7C1414KV18 Datasheet PDF - Cypress Semiconductor

Part Number CY7C1414KV18
Description 36-Mbit QDR II SRAM Two-Word Burst Architecture
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
36-Mbit QDR® II SRAM Two-Word
Burst Architecture
36-Mbit QDR® II SRAM Two-Word Burst Architecture
Features
Separate independent read and write data ports
Supports concurrent transactions
333 MHz clock for high bandwidth
Two-word burst on all accesses
Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Single multiplexed address input bus latches address inputs
for both read and write ports
Separate port selects for depth expansion
Synchronous internally self-timed writes
QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Available in × 9, × 18, and × 36 configurations
Full data coherency, providing most current data
Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free Packages
Variable drive HSTL output buffers
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1425KV18 – 4M × 9
CY7C1412KV18 – 2M × 18
CY7C1414KV18 – 1M × 36
Functional Description
The CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18
are 1.8 V synchronous pipelined SRAMs, equipped with QDR II
architecture. QDR II architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II architecture has separate data inputs and
data outputs to completely eliminate the need to “turnaround” the
data bus that exists with common I/O devices. Access to each
port is through a common address bus. Addresses for read and
write addresses are latched on alternate rising edges of the input
(K) clock. Accesses to the QDR II read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with two 9-bit
words (CY7C1425KV18), 18-bit words (CY7C1412KV18), or
36-bit words (CY7C1414KV18) that burst sequentially into or out
of the device. Because data can be transferred into and out of
the device on every rising edge of both input clocks (K and K and
C and C), memory bandwidth is maximized while simplifying
system design by eliminating bus turnarounds.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 300 MHz 250 MHz Unit
333 300 250 MHz
× 9 730 680 590 mA
× 18 750 700 610
× 36 910 850 730
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57825 Rev. *N
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 16, 2016

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CY7C1414KV18 equivalent
CY7C1425KV18
CY7C1412KV18
CY7C1414KV18
Pin Configurations
The pin configurations for CY7C1425KV18, CY7C1412KV18, and CY7C1414KV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1425KV18 (4M × 9)
12345678
A
CQ NC/72M
A
WPS
NC
K NC/144M RPS
B
NC NC NC
A NC/288M K
BWS0
A
C NC NC NC VSS A A A VSS
D NC D5 NC VSS VSS VSS VSS VSS
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
N NC D8 NC VSS A A A VSS
P NC NC Q8 A A C A A
R
TDO
TCK
A
A
A
C
A
A
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-57825 Rev. *N
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Featured Datasheets

Part NumberDescriptionMFRS
CY7C1414KV18The function is 36-Mbit QDR II SRAM Two-Word Burst Architecture. Cypress SemiconductorCypress Semiconductor

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