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PDF CY7C1411KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1411KV18 | |
| Descripción | 36-Mbit QDR II SRAM Four-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1411KV18/CY7C1426KV18
CY7C1413KV18/CY7C1415KV18
36-Mbit QDR® II SRAM Four-Word
Burst Architecture
36-Mbit QDR® II SRAM Four-Word Burst Architecture
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 333 MHz clock for high bandwidth
■ Four-word burst for reducing address bus frequency
■ Double data rate (DDR) Interfaces on both read and write ports
(data transferred at 666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■ Single multiplexed address input bus latches address inputs
for read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR® II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■ Available in × 8, × 9, × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ Variable drive HSTL output buffers
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1411KV18 – 4M × 8
CY7C1426KV18 – 4M × 9
CY7C1413KV18 – 2M × 18
CY7C1415KV18 – 1M × 36
Functional Description
The CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and
CY7C1415KV18 are 1.8 V synchronous pipelined SRAMs,
equipped with QDR II architecture. QDR II architecture consists
of two separate ports: the read port and the write port to access
the memory array. The read port has dedicated data outputs to
support read operations and the write port has dedicated data
inputs to support write operations. QDR II architecture has
separate data inputs and data outputs to completely eliminate
the need to “turnaround” the data bus that exists with common
I/O devices. Each port can be accessed through a common
address bus. Addresses for read and write addresses are
latched on alternate rising edges of the input (K) clock. Accesses
to the QDR II read and write ports are independent of one
another. To maximize data throughput, both read and write ports
are equipped with DDR interfaces. Each address location is
associated with four 8-bit words (CY7C1411KV18), 9-bit words
(CY7C1426KV18), 18-bit words (CY7C1413KV18), or 36-bit
words (CY7C1415KV18) that burst sequentially into or out of the
device. Because data can be transferred into and out of the
device on every rising edge of both input clocks (K and K and C
and C), memory bandwidth is maximized while simplifying
system design by eliminating bus ‘turnarounds’.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 300 MHz
333 300
× 8 Not Offered 520
× 9 560
520
× 18 570
540
× 36 790
730
250 MHz
250
460
460
470
640
Unit
MHz
mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57826 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 16, 2016
1 page  
CY7C1411KV18/CY7C1426KV18
CY7C1413KV18/CY7C1415KV18
Pin Configurations
The pin configurations for CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 follows. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1411KV18 (4M × 8)
1 2 3 4 5 6 7 8 9 10
A
CQ NC/72M
A
WPS
NWS1
K NC/144M RPS
A
A
B
NC NC NC
A NC/288M K
NWS0
A
NC NC
C NC NC NC VSS A NC A VSS NC NC
D NC D4 NC VSS VSS VSS VSS VSS NC NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
N NC D7 NC VSS A A A VSS NC NC
P NC NC Q7 A A C A A NC NC
R
TDO
TCK
A
A
A
C
A
A
A TMS
CY7C1426KV18 (4M × 9)
12345678
A
CQ NC/72M
A
WPS
NC
K NC/144M RPS
B
NC NC NC
A NC/288M K
BWS0
A
C NC NC NC VSS A NC A VSS
D NC D5 NC VSS VSS VSS VSS VSS
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
N NC D8 NC VSS A A A VSS
P NC NC Q8 A A C A A
R
TDO
TCK
A
A
A
C
A
A
Note
1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
9
A
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
A
10
A
NC
NC
NC
D3
NC
NC
VREF
Q2
NC
NC
NC
NC
D0
TMS
11
CQ
Q3
D3
NC
Q2
NC
NC
ZQ
D1
NC
Q0
D0
NC
NC
TDI
11
CQ
Q4
D4
NC
Q3
NC
NC
ZQ
D2
NC
Q1
D1
NC
Q0
TDI
Document Number: 001-57826 Rev. *K
Page 5 of 33
5 Page 
CY7C1411KV18/CY7C1426KV18
CY7C1413KV18/CY7C1415KV18
Truth Table
The truth table for CY7C1411KV18, CY7C1426KV18, CY7C1413KV18, and CY7C1415KV18 follows.[2, 3, 4, 5, 6, 7]
Operation
K RPS WPS
DQ
DQ
DQ
DQ
Write cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L–H
H[8] L[9] D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Read cycle:
L–H L[9] X Q(A) at C(t + 1) Q(A + 1) at C(t + 2) Q(A + 2) at C(t + 2) Q(A + 3) at C(t + 3)
Load address on the rising
edge of K; wait one and a
half cycle; read data on
two consecutive C and C
rising edges.
NOP: No operation
L–H H H D = X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
Standby: Clock stopped Stopped X X Previous state Previous state
Previous state
Previous state
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Document Number: 001-57826 Rev. *K
Page 11 of 33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C1411KV18.PDF ] | |
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