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What is CY7C1648KV18?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "144-Mbit DDR II+ SRAM Two-Word Burst Architecture".


CY7C1648KV18 Datasheet PDF - Cypress Semiconductor

Part Number CY7C1648KV18
Description 144-Mbit DDR II+ SRAM Two-Word Burst Architecture
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY7C1648KV18
CY7C1650KV18
144-Mbit DDR II+ SRAM Two-Word
Burst Architecture (2.0 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Features
144-Mbit density (8 M × 18, 4 M × 36)
450-MHz clock for high bandwidth
Two-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
900 MHz) at 450 MHz
Available in 2.0-clock cycle latency
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Data valid pin (QVLD) to indicate valid data on the output
Synchronous internally self-timed writes
DDR II+ operates with 2.0-cycle read latency when DOFF is
asserted high
Operates similar to DDR I device with one cycle read latency
when DOFF is asserted low
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
Supports both 1.5 V and 1.8 V I/O supply
High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1648KV18 – 8 M × 18
CY7C1650KV18 – 4 M × 36
Functional Description
The CY7C1648KV18, and CY7C1650KV18 are 1.8-V
synchronous pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two18-bit words
(CY7C1648KV18), or 36-bit words (CY7C1650KV18) that burst
sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
450 MHz 400 MHz
450 400
× 18 Not Offered 730
× 36 980
900
Unit
MHz
mA
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44061 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 18, 2015

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CY7C1648KV18 equivalent
CY7C1648KV18
CY7C1650KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
LD
Input Output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the K and K clocks during read operations. When read access is
deselected, Q[x:0] are automatically tristated.
CY7C1648KV18 DQ[17:0]
CY7C1650KV18 DQ[35:0]
Input- Synchronous load. Sampled on the rising edge of the K clock. This input is brought low when a bus
Synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
BWS0,
BWS1,
BWS2,
BWS3
Input- Byte write select (BWS) 0, 1, 2, and 3 Active low. Sampled on the rising edge of the K and K clocks
Synchronous during write operations. Used to select which byte is written into the device during the current portion of
the write operations. Bytes not written remain unaltered.
CY7C1648KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1650KV18  BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a BWS ignores the
corresponding byte of data and it is not written into the device.
A Input- Address inputs. Sampled on the rising edge of the K clock during active read and write operations.
Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 8 M × 18 (2 arrays each of 4 M × 18) for CY7C1648KV18, and 4 M × 36 (2 arrays each of
2 M × 36) for CY7C1650KV18.
R/W Input- Synchronous read or write input. When LD is low, this input designates the access type (read when
Synchronous R/W is high, write when R/W is low) for loaded address. R/W must meet the setup and hold times around
edge of K.
QVLD
Valid output Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
K Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K Input Clock Negative input clock input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0].
CQ Echo Clock Synchronous echo clock outputs. This is a free-running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
CQ Echo Clock Synchronous echo clock outputs. This is a free-running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
DOFF
Input
PLL turn off Active low. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull-up through a 10 kor less pull-up resistor. The device behaves in DDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with DDR I timing.
TDO
Output Test data-out (TDO) pin for JTAG.
TCK
Input Test clock (TCK) pin for JTAG.
TDI Input Test data-in (TDI) pin for JTAG.
TMS
Input Test mode select (TMS) pin for JTAG.
NC N/A Not connected to the die. Can be tied to any voltage level.
Document Number: 001-44061 Rev. *K
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Part NumberDescriptionMFRS
CY7C1648KV18The function is 144-Mbit DDR II+ SRAM Two-Word Burst Architecture. Cypress SemiconductorCypress Semiconductor

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