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PDF CY7C1150KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1150KV18 | |
| Descripción | 18-Mbit DDR II+ SRAM Two-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1148KV18/CY7C1150KV18
18-Mbit DDR II+ SRAM Two-Word
Burst Architecture (2.0 Cycle Read Latency)
18-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
Features
■ 18-Mbit density (1M × 18, 512K × 36)
■ 450-MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at
900 MHz) at 450 MHz
■ Available in 2.0 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.0 cycle read latency when DOFF is
asserted HIGH
■ Operates similar to DDR I device with one cycle read latency
when DOFF is asserted LOW
■ Core VDD = 1.8V ± 0.1 V; I/O VDDQ = 1.4 V to VDD[1]
❐ Supports both 1.5 V and 1.8 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C1148KV18 – 1M × 18
CY7C1150KV18 – 512K × 36
Functional Description
The CY7C1148KV18, and CY7C1150KV18 are 1.8 V
Synchronous Pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two 18-bit words
(CY7C1148KV18), or 36-bit words (CY7C1150KV18) that burst
sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
450 MHz 400 MHz Unit
450 400 MHz
× 18 560
510 mA
× 36 700
640
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4 V to VDD.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58912 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 19, 2016
1 page  
CY7C1148KV18/CY7C1150KV18
Pin Definitions
Pin Name
DQ[x:0]
LD
BWS0,
BWS1,
BWS2,
BWS3
A
R/W
QVLD
K
K
CQ
CQ
ZQ
DOFF
I/O Pin Description
Input output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the K and K clocks during read operations. When read access is deselected,
Q[x:0] are automatically tri-stated.
CY7C1148KV18 DQ[17:0]
CY7C1150KV18 DQ[35:0]
Input- Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus
synchronous cycle sequence is defined. This definition includes address and read/write direction. All transactions
operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.
Input- Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1148KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1150KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
Input- Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.
synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is
organized as 1M x 18 (2 arrays each of 512K x 18) for CY7C1148KV18, and 512K x 36 (2 arrays each
of 256K x 36) for CY7C1150KV18.
Input- Synchronous Read or Write Input. When LD is LOW, this input designates the access type (read when
synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
Input clock
Input clock
Echo clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0].
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
Echo clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Input
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 k or less pull up resistor. The device behaves in DDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
Document Number: 001-58912 Rev. *H
Page 5 of 29
5 Page 
CY7C1148KV18/CY7C1150KV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
Remember that the TAP controller clock can only operate at a
frequency up to 20 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output undergoes a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that is captured. Repeatable results
may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #47.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Document Number: 001-58912 Rev. *H
Page 11 of 29
11 Page | ||
| Páginas | Total 29 Páginas | |
| PDF Descargar | [ Datasheet CY7C1150KV18.PDF ] | |
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