CY7C2564XV18 Datasheet PDF - Cypress Semiconductor
| Part Number | CY7C2564XV18 | |
| Description | 72-Mbit QDR II+ Xtreme SRAM Two-Word Burst Architecture | |
| Manufacturers | Cypress Semiconductor | |
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CY7C2562XV18/CY7C2564XV18
72-Mbit QDR® II+ Xtreme SRAM Two-Word
Burst Architecture (2.5 Cycle Read Latency) with ODT
72-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT
Features
■ Separate independent read and write data ports
❐ Supports concurrent transactions
■ 450 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces on both read and write ports
(data transferred at 900 MHz) at 450 MHz
■ Available in 2.5 clock cycle latency
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ On-Die Termination (ODT) feature
❐ Supported for D[x:0], BWS[x:0], and K/K inputs
■ Single multiplexed address input bus latches address inputs
for both read and write ports
■ Separate port selects for depth expansion
■ Synchronous internally self-timed writes
■ QDR™-II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
■ Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
■ Available in × 18, and × 36 configurations
■ Full data coherency, providing most current data
■ Core VDD = 1.8 V ± 0.1 V; VDDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
■ HSTL inputs and variable drive HSTL output buffers
■ Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
■ CY7C2564XV18 offered in both Pb-free and non Pb-free
packages and CY7C2562XV18 offered in Pb-free package
only.
■ JTAG 1149.1 compatible test access port
■ Phase-locked loop (PLL) for accurate data placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C2562XV18 – 4M × 18
CY7C2564XV18 – 2M × 36
Functional Description
The CY7C2562XV18 and CY7C2564XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR™-II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common devices. Access to each port is through a
common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ read and write ports are completely
independent of one another. To maximize data throughput, both
read and write ports are equipped with DDR interfaces. Each
address location is associated with two 18-bit words
(CY7C2562XV18), or 36-bit words (CY7C2564XV18) that burst
sequentially into or out of the device. Because data can be
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
These devices have an on-die termination (ODT) feature
supported
eliminate
efxotrernDa[xl:0t]e, rmBWinaSt[ixo:0n],
and K/K
resistors,
inputs,
reduce
which helps
cost, reduce
board area, and simplify board routing.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
450 MHz 366 MHz Unit
450 366 MHz
× 18 1205
970 mA
× 36 1445
1165
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70204 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 12, 2016
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CY7C2562XV18/CY7C2564XV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
WPS
BWS0,
BWS1,
BWS2,
BWS3
Input- Data Input Signals. Sampled on the rising edge of K and K clocks during valid write operations.
Synchronous CY7C2562XV18 D[17:0]
CY7C2564XV18 D[35:0]
Input- Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
Input- Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the
write operations. Bytes not written remain unaltered.
CY7C2562XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C2564XV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A Input- Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks during
Synchronous active read and write operations. These address inputs are multiplexed for both read and write
operations. Internally, the device is organized as 4M × 18 (2 arrays each of 2M × 18) for CY7C2562XV18,
and 2M × 36 (2 arrays each of 1M × 36) for CY7C2564XV18. Therefore, only 21 address inputs are
needed to access the entire memory array for CY7C2562XV18, and 20 address inputs for
CY7C2564XV18. These inputs are ignored when the appropriate port is deselected. The Address pins
(A) can be assigned any bit order.
Q[x:0]
RPS
Output- Data Output Signals. These pins drive out the requested data during a read operation. Valid data is
Synchronous driven out on the rising edge of the K and K clocks during read operations. When the read port is
deselected, Q[x:0] are automatically tristated.
CY7C2562XV18 Q[17:0]
CY7C2564XV18 Q[35:0]
Input- Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active,
Synchronous a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access
is allowed to complete and the output drivers are automatically tristated following the next rising edge of
the K clock. Each read access consists of a burst of two sequential transfers.
QVLD
ODT [2]
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
On-Die
Termination
input pin
On-Die Termination Input. This pin is used for on-die termination (ODT) of the input signals. ODT range
selection is made during power up initialization. A LOW on this pin selects a low range that follows
RQ/3.33 for 175 < RQ < 350(where RQ is the resistor tied to ZQ pin)A HIGH on this pin selects a
high range that follows RQ/1.66 for 175 < RQ < 250 (where RQ is the resistor tied to ZQ pin). When
left floating, a high range termination value is selected by default.
K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device
and to drive out data through Q[x:0].
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 23.
Note
2. On-die termination (ODT) feature is supported for D[x:0], BWS[x:0], and K/K inputs.
Document Number: 001-70204 Rev. *F
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| Part Number | Description | MFRS |
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