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PDF CY7C1265XV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1265XV18 | |
| Descripción | 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1263XV18
CY7C1265XV18
36-Mbit QDR® II+ Xtreme SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency)
36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
■ Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
■ 633 MHz Clock for High Bandwidth
■ Four-word Burst for Reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1266 MHz) at 633 MHz
■ Available in 2.5 Clock Cycle Latency
■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■ Data Valid Pin (QVLD) to indicate Valid Data on the Output
■ Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
■ Separate Port selects for Depth Expansion
■ Synchronous Internally Self-timed Writes
■ QDR® II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
■ Operates similar to QDR I Device with one Cycle Read Latency
when DOFF is asserted LOW
■ Available in × 18 and × 36 Configurations
■ Full Data Coherency, providing Most Current Data
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
■ HSTL Inputs and Variable Drive HSTL Output Buffers
■ Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)
■ Offered in Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
■ Phase-Locked Loop (PLL) for Accurate Data Placement
Configurations
With Read Cycle Latency of 2.5 cycles:
CY7C1263XV18 – 2 M × 18
CY7C1265XV18 – 1 M × 36
Functional Description
The CY7C1263XV18, and CY7C1265XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ Xtreme read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words (CY7C1263XV18), or 36-bit words (CY7C1265XV18) that
burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum Operating Frequency
Maximum Operating Current
Description
633 MHz 600 MHz Unit
633 600 MHz
× 18 1165
1100
mA
× 36 1660
1570
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-70328 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 20, 2015
1 page  
CY7C1263XV18
CY7C1265XV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
WPS
BWS0,
BWS1,
BWS2,
BWS3
Input- Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C1263XV18 D[17:0]
CY7C1265XV18 D[35:0]
Input- Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
Input- Byte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1263XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1265XV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A Input- Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2 M × 18 (4 arrays each of 512 K × 18) for CY7C1263XV18 and 1 M × 36 (4 arrays each of 256 K × 36)
for CY7C1265XV18. Therefore, only 19 address inputs are needed to access the entire memory array for
CY7C1263XV18 and 18 address inputs for CY7C1265XV18. These inputs are ignored when the
appropriate port is deselected. The address pins (A) can be assigned any bit order.
Q[x:0]
RPS
Outputs- Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tristated.
CY7C1263XV18 Q[17:0]
CY7C1265XV18 Q[35:0]
Input- Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
K Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme. The timings for the echo clocks are shown in the Switching Characteristics on
page 24.
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme.The timings for the echo clocks are shown in the Switching Characteristics on
page 24.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
Document Number: 001-70328 Rev. *E
Page 5 of 30
5 Page 
CY7C1263XV18
CY7C1265XV18
Write Cycle Descriptions
The write cycle description table for CY7C1265XV18 follows. [12, 13]
BWS0 BWS1 BWS2 BWS3 K
L L L L L–H
K Comments
– During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Notes
12. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
13.
Is based
cycle, as
on a
long
write cycle that was initiated in accordance with above
as the setup and hold requirements are achieved.
Truth
Table
on
page
9.
BWS0,
BWS1,BWS2,
BWS3
can
be
altered
on
different
portions
of
a
write
Document Number: 001-70328 Rev. *E
Page 11 of 30
11 Page | ||
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