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PDF CY7C1618KV18 Data sheet ( Hoja de datos )
| Número de pieza | CY7C1618KV18 | |
| Descripción | 144-Mbit DDR II SRAM Two-Word Burst Architecture | |
| Fabricantes | Cypress Semiconductor | |
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CY7C1618KV18/CY7C1620KV18
144-Mbit DDR II SRAM Two-Word
Burst Architecture
144-Mbit DDR II SRAM Two-Word Burst Architecture
Features
■ 144-Mbit density (8M × 18, 4M × 36)
■ 333 MHz clock for high bandwidth
■ Two-word burst for reducing address bus frequency
■ Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Synchronous internally self-timed writes
■ DDR II operates with 1.5-cycle read latency when DOFF is
asserted high
■ Operates similar to DDR I device with one cycle read latency
when DOFF is asserted low
■ 1.8-V core power supply with high-speed transceiver logic
(HSTL) inputs and outputs
■ Variable drive HSTL output buffers
■ Expanded HSTL output voltage (1.4 V–VDD)
❐ Supports both 1.5-V and 1.8-V I/O supply
■ Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 × 17 × 1.4 mm)
■ Offered in Pb-free packages
■ JTAG 1149.1 compatible test access port
■ Phase locked loop (PLL) for accurate data placement
Configuration
CY7C1618KV18 – 8M × 18
CY7C1620KV18 – 4M × 36
Functional Description
The CY7C1618KV18, and CY7C1620KV18 are 1.8-V
synchronous pipelined SRAM equipped with DDR II architecture.
The DDR II consists of an SRAM core with advanced
synchronous peripheral circuitry and a 1-bit burst counter.
Addresses for read and write are latched on alternate rising
edges of the input (K) clock. Write data is registered on the rising
edges of both K and K. Read data is driven on the rising edges
of C and C if provided, or on the rising edge of K and K if C/C are
not provided. On CY7C1618KV18 and CY7C1620KV18, the
burst counter takes in the least significant bit of the external
address and bursts two 18-bit words in the case of
CY7C1618KV18 and two 36-bit words in the case of
CY7C1620KV18 sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 300 MHz 250 MHz Unit
333 300 250 MHz
× 18 650
610 Not Offered mA
× 36 790 Not Offered 660
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-44274 Rev. *M
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 9, 2016
1 page  
CY7C1618KV18/CY7C1620KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
LD
Input Output- Data input output signals: Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is
driven out on the rising edge of both the C and C clocks during read operations or K and K when in single
clock mode. When read access is deselected, Q[x:0] are automatically tristated.
CY7C1618KV18 DQ[17:0]
CY7C1620KV18 DQ[35:0]
Input- Synchronous load: This input is brought low when a bus cycle sequence is defined. This definition
Synchronous includes address and read and write direction. All transactions operate on a burst of 2 data.
BWS0,
BWS1,
BWS2,
BWS3
Input- Byte write select (BWS) 0, 1, 2, and 3 Active low: Sampled on the rising edge of the K and K clocks
Synchronous during write operations. Used to select which byte is written into the device during the current portion of
the write operations. Bytes not written remain unaltered.
CY7C1618KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1620KV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the byte write selects are sampled on the same edge as the data. Deselecting a BWS ignores the
corresponding byte of data and it is not written into the device.
A, A0
Input- Address inputs: These address inputs are multiplexed for both read and write operations. Internally,
Synchronous the device is organized as 8M × 18 (2 arrays each of 4M × 18) for CY7C1618KV18, and 4M × 36 (2
arrays each of 2M × 36) for CY7C1620KV18.
CY7C1618KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 23 address inputs are needed to access the entire memory array.
CY7C1620KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion
internally. 22 address inputs are needed to access the entire memory array. All the address inputs are
ignored when the appropriate port is deselected.
R/W Input- Synchronous read or write input: When LD is low, this input designates the access type (read when
Synchronous R/W is high, write when R/W is low) for loaded address. R/W must meet the setup and hold times around
edge of K.
C Input Clock Positive input clock for output data: C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
C Input Clock Negative input clock for output data: C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See application example for further details.
K Input Clock Positive input clock input: The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K Input Clock Negative input clock input: K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ Output Clock CQ referenced with respect to C: This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
CQ Output Clock CQ referenced with respect to C: This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Document Number: 001-44274 Rev. *M
Page 5 of 32
5 Page 
CY7C1618KV18/CY7C1620KV18
Write Cycle Descriptions
The write cycle description table for CY7C1620KV18 follows: [10, 11]
BWS0 BWS1 BWS2 BWS3 K
L L L L L–H
K Comments
– During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L L L L – L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H H H H L–H – No data is written into the device during this portion of a write operation.
H H H H – L–H No data is written into the device during this portion of a write operation.
Notes
10. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
11.
Is based on a write
write cycle, as long
cycle that was initiated in accordance with the Truth
as the setup and hold requirements are achieved.
Table
on
page
9.
BWS0,
BWS1,
BWS2,
and
BWS3
can
be
altered
on
different
portions
of
a
Document Number: 001-44274 Rev. *M
Page 11 of 32
11 Page | ||
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