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What is CY7C1319KV18?

This electronic component, produced by the manufacturer "Cypress Semiconductor", performs the same function as "18-Mbit DDR II SRAM Four-Word Burst Architecture".


CY7C1319KV18 Datasheet PDF - Cypress Semiconductor

Part Number CY7C1319KV18
Description 18-Mbit DDR II SRAM Four-Word Burst Architecture
Manufacturers Cypress Semiconductor 
Logo Cypress Semiconductor Logo 


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CY7C1319KV18/CY7C1321KV18
18-Mbit DDR II SRAM
Four-Word Burst Architecture
18-Mbit DDR II SRAM Four-Word Burst Architecture
Features
18-Mbit density (1M × 18, 512K × 36)
333-MHz clock for high bandwidth
Four-word burst for reducing address bus frequency
Double data rate (DDR) interfaces (data transferred at
666 MHz) at 333 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
Synchronous internally self-timed writes
DDR II operates with 1.5 cycle read latency when DOFF is
asserted HIGH
Operates similar to DDR I device with one cycle read latency
when DOFF is asserted LOW
1.8 V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4 V–VDD)
Supports both 1.5 V and 1.8 V I/O supply
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Phase locked loop (PLL) for accurate data placement
Configurations
CY7C1319KV18 – 1M × 18
CY7C1321KV18 – 512K × 36
Functional Description
CY7C1319KV18 and CY7C1321KV18 are 1.8 V Synchronous
Pipelined SRAMs equipped with DDR II architecture. The DDR
II consists of an SRAM core with advanced synchronous
peripheral circuitry and a two-bit burst counter. Addresses for
read and write are latched on alternate rising edges of the input
(K) clock. Write data is registered on the rising edges of both K
and K. Read data is driven on the rising edges of C and C if
provided, or on the rising edge of K and K if C/C are not provided.
For CY7C1319KV18 and CY7C1321KV18, the burst counter
takes in the least two significant bits of the external address and
bursts four 18-bit words in the case of CY7C1319KV18, and four
36-bit words in the case of CY7C1321KV18, sequentially into or
out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
For a complete list of related documentation, click here.
Selection Guide
Maximum operating frequency
Maximum operating current
Description
333 MHz 250 MHz Unit
300 250 MHz
× 18 370
320 mA
× 36 440
370
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-58906 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 19, 2016

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CY7C1319KV18 equivalent
CY7C1319KV18/CY7C1321KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
LD
Input/Output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
synchronous operations. These pins drive out the requested data during a read operation. Valid data is driven out on
the rising edge of both the C and C clocks during read operations or K and K when in single clock mode.
When read access is deselected, Q[x:0] are automatically tristated.
CY7C1319KV18 DQ[17:0]
CY7C1321KV18 DQ[35:0]
Input- Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
synchronous includes address and read/write direction. All transactions operate on a burst of four data (two clock
periods of bus activity).
BWS0,
BWS1,
BWS2,
BWS3
Input- Byte write select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and K clocks during
synchronous write operations. Used to select which byte is written into the device during the current portion of the
Write operations. Bytes not written remain unaltered.
CY7C1319KV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1321KV18  BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3
controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A, A0, A1
Input- Address inputs. These address inputs are multiplexed for both read and write operations. Internally,
synchronous the device is organized as 1M × 18 (4 arrays each of 256K × 18) for CY7C1319KV18, and 512K × 36
(4 arrays each of 128K × 36) for CY7C1321KV18.
CY7C1319KV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a
linear fashion. 20 address inputs are needed to access the entire memory array.
CY7C1321KV18 – A0 and A1 are the inputs to the burst counter. These are incremented internally in a
linear fashion. 19 address inputs are needed to access the entire memory array.
R/W Input- Synchronous read/write input. When LD is LOW, this input designates the access type (read when
synchronous R/W is HIGH, write when R/W is LOW) for the loaded address. R/W must meet the setup and hold times
around the edge of K.
C Input clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 8 for more information.
C Input clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board
back to the controller. See Application Example on page 8 for more information.
K Input clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K Input clock Negative input clock input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ Output clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in Switching Characteristics on page 24.
CQ Output Clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in Switching Characteristics on page 24.
ZQ Input Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which
enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
Document Number: 001-58906 Rev. *J
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Part NumberDescriptionMFRS
CY7C1319KV18The function is 18-Mbit DDR II SRAM Four-Word Burst Architecture. Cypress SemiconductorCypress Semiconductor

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