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PDF HMC1144 Data sheet ( Hoja de datos )
| Número de pieza | HMC1144 | |
| Descripción | Medium Power Amplifier | |
| Fabricantes | Analog Devices | |
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Data Sheet
40 GHz to 70 GHz, GaAs, pHEMT, MMIC,
Medium Power Amplifier
HMC1144
FEATURES
Output power for 1 dB compression (P1dB): 21 dBm typical
Saturated output power (PSAT): 22 dBm typical
Gain: 19 dB typical
Output third-order intercept (IP3): 28 dBm typical
Supply voltage: 4 V at 320 mA
50 Ω matched input/output
Die size: 2.3 mm × 1.8 mm × 0.05 mm
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military and space
Telecommunications infrastructure
Fiber optics
GENERAL DESCRIPTION
The HMC1144 is a gallium arsenide (GaAs), pseudomorphic
high electron mobility transfer (pHEMT), monolithic microwave
integrated circuit (MMIC), distributed power amplifier that
operates from 40 GHz to 70 GHz. In the lower band of 40 GHz
to 50 GHz, the HMC1144 provides 19 dB (typical) of gain,
28 dBm output IP3, and 19.5 dBm of output power at 1 dB gain
compression. In the upper band of 50 GHz to 70 GHz, the
FUNCTIONAL BLOCK DIAGRAM
2 34 5
6
1 RFIN
HMC1144
RFOUT 7
12 11 10 9
Figure 1.
8
HMC1144 provides 19 dB (typical) of gain, 32 dBm output IP3,
and 21 dBm of output power at 1 dB gain compression. The
HMC1144 requires 320 mA from a 4 V supply. The HMC1144
amplifier inputs/outputs are internally matched to 50 Ω, facilitating
integration into multichip modules (MCMs). All data is taken
with the chip connected via two 0.025 mm (1 mil) wire bonds
of 0.076 mm (3 mil) minimal length.
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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1 page  
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VGG1A VDD1A VDD2A VDD3A
VDD4A
2 34 5
6
HMC1144
RFIN 1
HMC1144
TOP VIEW
(Not to Scale)
7 RFOUT
12 11 10 9
8
VGG1B
VDD1B VDD2B VDD3B
Figure 2. Pad Configuration
VDD4B
Table 4. Pad Function Descriptions
Pad No.
Mnemonic
Description
1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic.
2
VGG1A
Gate Control Pad for Alternate Bias Configuration. See Figure 4 for the interface schematic..
3 to 6
VDD1A to VDD4A Drain Bias Voltage Pads for the Amplifier. External bypass capacitors of 100 pF and 0.1 µF are required.
See Figure 5 for the interface schematic.
7
RFOUT
RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic.
8 to 11
VDD4B to VDD1B Drain Bias Voltage Pads for Alternate Bias Configuration. External bypass capacitors of 100 pF and 0.1 µF
are required for decoupling. See Figure 7 for the interface schematic.
12 VGG1B Gate Control Pad for the Amplifier. External bypass capacitors of 100 pF and 0.1 µF are required. See Figure 8
for the interface schematic.
Die Bottom GND
Die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic.
INTERFACE SCHEMATICS
RFIN
VDD1B TO VDD4B
Figure 3. RFIN Interface Schematic
Figure 7. VDD1B to VDD4B Interface Schematic
VGG1A
Figure 4. VGG1A Interface Schematic
VDD1A TO VDD4A
Figure 5. VDD1A to VDD4A Interface Schematic
VGG1B
Figure 8. VGG1B Interface Schematic
GND
Figure 9. GND Interface Schematic
RFOUT
Figure 6. RFOUT Interface Schematic
Rev. B | Page 5 of 15
5 Page 
Data Sheet
HMC1144
APPLICATIONS INFORMATION
The HMC1144 is a GaAs, pHEMT, MMIC power amplifier.
Capacitive bypassing is required for VDD1A through VDD4A and
VDD1B through VDD4B (see Figure 37). VGG1B is the gate bias
pad for all four gain stages. Apply a gate bias voltage to VGG1B
and use capacitive bypassing as shown in Figure 37.
All measurements for this device were taken using the typical
application circuit (see Figure 37) and configured as shown in
the assembly diagram (see Figure 39).
The following is the recommended bias sequence during
power-up:
1. Connect to ground.
2. Set the gate bias voltage to −2 V.
3. Set all the drain bias voltages, VDD = 4 V.
4. Increase the gate bias voltage to achieve a quiescent
current, IDD = 320 mA.
5. Apply the RF signal.
The following is the recommended bias sequence during
power-down:
1. Turn off the RF signal.
2. Decrease the gate bias voltage to −2 V to achieve
IDD = 0 mA (approximately).
3. Decrease all of the drain bias voltages to 0 V.
4. Increase the gate bias voltage to 0 V.
The VDD = 4 V and IDD = 320 mA bias conditions are the operating
points recommended to optimize the overall performance. Unless
otherwise noted, the data shown was taken using the recom-
mended bias condition. Operation of the HMC1144 at different
bias conditions may provide performance that differs from what
is shown in the Typical Performance Characteristics section.
Biasing the HMC1144 for higher drain current typically results
in higher P1dB, output IP3, and gain, but at the expense of
increased power consumption.
ALTERNATE BIASING CONFIGURATION
It is possible to bias the gate from the north (instead of the
south) and bias the drain from the south (instead of the north).
Although this alternate bias configuration was not measured
during production testing and was evaluated minimally during
product validation, it does offer flexibility in cases where it is
more convenient to have the gate and drain bias approach the
die from a different direction (see Figure 38).
In the alternate bias configuration, capacitive bypassing is
required for the VGG1A pad to which the bias voltage is applied,
as well as for all eight VDDxA/VDDxB pads.
VDD1A
VDD1B
VDD2A
VDD2B
VDD3A
VDD3B
VDD4A
VDD4B
RFIN
1A 1B
2A 2B
3A 3B
RFOUT
4A 4B
VGG1A
VGG1B
Figure 34. Simplified Block Diagram
Rev. B | Page 11 of 15
11 Page | ||
| Páginas | Total 15 Páginas | |
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