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PDF UPD7802 Data sheet ( Hoja de datos )
| Número de pieza | UPD7802 | |
| Descripción | HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER | |
| Fabricantes | NEC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UPD7802 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas | ||
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NEe Microcomputers, Inc.
NEe
},(PD7802
HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
WITH 6K ROM
PRODUCT DESCRIPTION
FEATURES
The NEC !,PD7802 is an advanced 8-bit general purpose single-chip microcomputer fabricated with
N-Channel Silicon Gate MOS technology.
The NEC !,PD7802 is intended to serve a broad spectrum of 8-bit designs ranging from enhanced
single chip applications extending into the multi-chip microprocessor range. All the basic func-
tional blocks - 6144 x 8 of ROM program memory, 64 x 8 of RAM data memory, 8-bit ALU, 48
I/O lines, Serial I/O port,12-bit timer,and clock generator are provided on-chip to enhance stand-
alone applications. Fully compatible with the industry standard 8080A bus structure, expanded
system operation can be easily implemented using any of the 8080A/8085A peripherals and
memory products. Total 'memory space can be increased to 64K bytes.
The powerful 140 instruction set coupled with 6K bytes of ROM program memory and 64 bytes
of RAM data memory greatly extends the range of single chip microcomputer applications. Five
level vectored interrupt capability combined with a 2 microsecond cycle time enable the !,PD7802
to compete with multi-chip microprocessor systems with the advantage that most of the support
functions are on--chip.
• NMOS Silicon Gate Technology Requiring +5V Supply
• Complete Single-Chip Microcomputer with On-Chip ROM, RAM and I/O
- 6K Bytes ROM
- 64 Bytes -RAM
- 48 I/O "Lines
• Internal 12-8it Programmable Timer
• On-Chip 1 MHz Serial Port
• Five Level Vectored, Prioritized Interrupt Structure
- Serial Port
- Timer
- 3 External Interrupts
• Bus Expansion Capabilities
- Fully 8080A Bus Compatible
- 58K Bytes External Memory Address Range
• On-Chip Clock Generator
• Wait State Capability
• Alternate Z80™ Type Register Set
• Powerful 140 Instruction Set
• 8 Address Modes; Including Auto-Increment/Decrement
• Multi-Level Stack Capabilities
• Fast 2 !,S Cycle Time
• Bus Sharing Capabilities
PIN CONFIGURATION
PE15
Vcc (+5V)
!/>OUT
PE14
DB7 PE13
DB6 4
PE12
DB5 5
PEn
DB4 6
PE10
DB3 7
PES
DB2 a
PEa
DBl 9
PE7
DBO 10
PE6
INT2 11
PE5
INTl 12
PE4
INTO -13
PE3
WAIT 14
PE2
MI
ViR
m5
15
16
17
IlPD
7802
PEl
PEo
PB7
PC7 la
PB6
PC6 19
PB5
PC5 20
PB4
PC4 21
44 PB3
PC3 22
43 PB2
PC2 23
42 PBl
PC, 24
41 PBO
PCa 26
40 PA7
SCK 26
39 PA6
SI 27
38 PA5
So 28
37 PA4
RESET 29
36 PA3
X2 30
35 PA2
Xl 31
34 PAl
VSS(OV) 32
33 PAO
277
1 page  
FUNCTIONAL TIMER OPERATION
DESCRIPTION
(CONT.)
j.l.PD7802
t-_o-oTO
TIMER BLOCK DIAGRAM
A programmable 12·bit timer is provided on-chip for measuring time intervals, generat-
ing pulses, and general time-related control functions. It is capable of measuring time
intervals from 4 J-lS to 16 ms in duration. The timer consists of a prescaler which
decrements a 12-bit counter at a fixed 4 J-lS rate. Count pulses are loaded into the
12-bit down counter through timer register (TMO and TM 11. Count-down operation is
initiated upon extension of the STM instruction when the contents of the down
counter are fully decremented and a borrow operation occurs, an interval interrupt
(INTTI is generated. At the same time, the contents of TMO and TM1 are reloaded
into the down-counter and countdown operation is resumed. Count operation may be
restarted or initialized with the STM instruction. The duration of the timeout may be
altered by loading new contents into the down counter.
The timer flip flop is set by the STM instruction and reset on a countdown operation.
Its output (TOI is available externally and may be used in a single pulse mode or general
external synchronization.
Timer interrupt (lNTII may be disabled through the interrupt.
SERIAL PORT OPERATION
~, "PCsrSAK
"
MCJ
QR
WR, RD.
SERIAL PORT BLOCK DIAGRAM
281
5 Page 
P. PD7802
INSTRUCTION GROUPS
MNEMONIC OPERANDS
NO.
C~OCK
BYTES CYCLES
OPERATION
a·BIT DATA TRANSFER
MOV
MOV
MOV
MOV
,vlOV
MOV
MVI
MVIW
MVIX
STAW
~OAW
STAX
~OAX
EXX
EX
B~OCK
SBCO
SOEO
SHLD
SSPO
LBCO
LOEO
LH~O
LSPO
PUSH
POP
LXI
TABLE
,l,A
A"l
sr, A
A, sr1
r, word
word, r
r, byte
we, byte
,pal, byta
wa
wa
,pa
,pa
word
word
word
word
word
word
word
word
rpl
rpl
rp, word
1 4 r1 +- A
1 4 A+- r1
2 10 sr-A
2 10 A-srl
4 17 r_ (word)
4 17 (word)-r
2 7 r +- byte
3 13 lv, wa) - byte
2 10 I,pall - byte
2 10 (V,wa)-A
2 10 A-(V,wa)
1 7 I,pa)-A
1 7 A-Irpa)
1 4 Exchange register sets
1 4 V, A~V,A
1 13IC+l) IDE)+ - IH~)+, C - C - 1
16-BIT DATA TRANSFER
4 20 Iword) - C, Iword + 1) - B
4 20 Iword) - E, Iword + 1) - 0
4 20 Iword) - L, Iword + 1) - H
4 20 Iword) - SPL, Iword + 1) - SPH
4 20 C - Iword), B - (word + 1)
4 20 E - Iword), 0 -Iword + 1)
4 20 ~ - Iword), H - (word + 1)
-4 20 SP~ -Iword), SPH - lword + 11
2 17 ISP - 1)- rplH, ISP - 2)- rpl~
2 15 rpl ~ - ISP)
rp'1.t:i - (SP + I), SP - SP + 2
3 10 rp -word
1 19 C-IPC + 2 + A)
B - IPC + 2 + A + 1)
SKIP
FLAGS
CONDITION CY Z
287
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet UPD7802.PDF ] | |
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