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What is UPD4164-1?

This electronic component, produced by the manufacturer "NEC", performs the same function as "65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY".


UPD4164-1 Datasheet PDF - NEC

Part Number UPD4164-1
Description 65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY
Manufacturers NEC 
Logo NEC Logo 


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Total 6 Pages



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No Preview Available ! UPD4164-1 datasheet, circuit

NEe Microcomputers, Inc.
65,536 x 1 BIT DYNAMIC
RANDOM ACCESS MEMORY
NEe
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,.,. PD4164-2
J.L PD4164-3
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DESCR IPTI ON
The NEC /lPD4164 is a 65,536 words by 1 bit Dynamic N-Channel MOS RAM designed
to operate from a single +5V power supply. The negative-voltage substrate bias is
internally generated - its operation is both automatic and transparent.
The /lPD4164 utilizes a double-poly-layer N-channel silicon gate process which provides
high storage cell density, high performance and high reliability.
The /lPD4164 uses a single transistor dynamic storage cell and advanced dynamic
circuitry throughout, including the 512 sense amplifiers, which assures that power
dissipation is minimized. Refresh characteristics have been chosen to maximize yield
(low cost to user) while maintaining compatibility between Dynamic RAM generations.
The /lPD4164 three-state output is controlled by CAS, independent of RAS. After a
valid read or read-modify-write cycle, data is held on the output by holding CAS low.
The data out pin is returned to the high impedance state by returning CAS to a high
state. The /lPD4164 hidden refresh feature allows CAS to be held low to maintain
output data while RAS is used to execute RAS only refresh cycles.
Refreshing is accomplished by performing RA"S" only refresh cycles, hidden refresh
cycles, or normal read or write cycles on the 128 address combinations of AO through
A6 during a 2 ms period.
FEATURES
Multiplexed address inputs permit the /lPD4164 to be packaged in the standard 16
pin dual-in-line package. The 16 pin package provides the highest system bit densities
and is compatible with widely available automated handling equipment.
High Memory Density
• MUltiplexed Address Inputs
• Single +5V Supply
• On Chip Substrate Bias Generator
• Access Time: /lPD4164-1 - 250 ns
/lPD4164-2 - 200 ns
/lPD4164-3 - 150 ns
• Read, Write Cycle Time: /lPD4164-1 - 410 ns
/lPD4164-2 - 335 ns
/lPD4164-3 - 270 ns
• Low Power Dissipation: 250 mW (Active); 28 mW (Standby)
• Non-Latched Output is Three-State, TTL Compatible
• Read, Write, Read-Write; Read-Modify-Write, RAS Only Refresh, and Page Mode
Capability
• All Inputs TTL Compatible, and Low Input Capacitance
• 128 Refresh Cycles (AO-A6 Pins for Refresh Address)
• CAS Controlled Output Allows Hidden Refresh
• Available in Both Ceramic and Plastic 16 Pin Packages
PIN CONFIGURATION
NC
DIN
WE
RAS
AO
A2
A1
VCC
VSS
CAS
DOUT
A6
A3
A4
A5
A7
AO-A7
RAS
CAS
WE
DIN
DOUT
VCC
VSS
NC
PIN NAMES
Address Inputs
Row Address Strobe
Col umn Address Strobe
Write Enable
Data Input
Data Output
Power Supply (+5V)
Ground
No Connection
47

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UPD4164-1 equivalent
~PD4164
TIMING WAVEFORMS
(CONT.)
··iiA$.ONLY" REFRESH CYCLE
RAS
ADDREsses
CAS
DOUT
V 1HC_
"11.._
V IM _
"11.._
"IHC
V'L
"OH-
"01.._ -------------------------OP'N----------------------------
HIDDEN REFRESH CYCLE
II
RAS
V1HC_ ---++-"':'::::::.10.
V IL _
V 1H _
ADDRESSES V
. 11..-·
PAGE MODE READ CYCLE
RAS
CAS
"11.._
ADDRESSES
V 1H _
"11.._
WRITE
o'N
V11.._
VIH _
11 11._
PAGE MODE WRITE CYCLE
51


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Part Details

On this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for UPD4164-1 electronic component.


Information Total 6 Pages
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Featured Datasheets

Part NumberDescriptionMFRS
UPD4164-1The function is 65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY. NECNEC
UPD4164-2The function is 65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY. NECNEC
UPD4164-3The function is 65536 x 1-BIT DYNAMIC RANDOM ACCESS MEMORY. NECNEC

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