UPD2118-2 Datasheet PDF - NEC
Part Number | UPD2118-2 | |
Description | 16384 x 1 BIT DYNAMIC MOS RANDOM ACCESS MEMORY | |
Manufacturers | NEC | |
Logo | ||
There is a preview and UPD2118-2 download ( pdf file ) link at the bottom of this page. Total 9 Pages |
Preview 1 page No Preview Available ! NEe Microcomputers, Inc.
16384 x 1 BIT DYNAMIC MOS
RANDOM ACCESS MEMORY
NEe
,uPD2118
,uPD2118-2
JI. PD2118-3
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DESCR IPTION
ThepPD2118 is a single +5V power supply, 16384 word by 1 bit Dynamic MOS RAM.
The IlPD2118 achieves high speed with low power dissipation by the use of single tran·
sistor dynamic storage cell design and advanced dynamic circuitry. This circuit design
results in the minimizing of current transients typical of dynamic RAMS. This in turn
II
results in high noise immunity of the IlPD2118 in a system environment. By using a
multiplexing technique, the IlPD2118 can be packaged in an industry standard 16·Pin
Dip utilizing 7 address input pins for the 14 address bits required. The two 7 bit address
words are referred to as the ROWand COLUMN address. Two TTL clocks, ROW address
strobe (RAS) and COLUMN address strobe (CAS") latch these two words into the
IlPD2118. Non·critical timing requirements for RAS and CAS permit high systems per·
formance without placing difficult constraints upon the multiplexing control circuitry.
The IlPD2118 has a three·state output controlled by CAS, independent of RAS. Follow·
ing a valid read or read·modify·write cycle, data will be held in the output by holding
CAS low. Returning CAS to a high state will result in the data out pin reverting to the
high impedance mode. Use of this CAS controlled output means that the IlPD2118 can
perform hidden refresh by holding CAS low to maintain latch data output while using
RAS to execute RAS·only·refresh cycles.
The use of single transistor storage cell circuitry ~equires that data be periodically
refreshed. Refreshing can be accomplished by performing RAS·only·refresh cycles,
hidden refresh cycles or normal read or write cycles on each of the 128 address com-
binations of AO through A6 during a 2 ms period. The write cycle will refresh stored
data on all bits of the selected row, except that the bit which is addressed will be mod·
ified to reflect the data input.
FEATURES
• Single+5VSupply,±10%Tolerance
• Low Power: 138 mW Max Operating
16 mW Max Standby
• Low VDD Current Transients
• All Inputs, Including Clocks, TTL Compatible
•• Non·Latched Output is Three·State
• RAS·Only·Refresh
• 128 Refresh Cycles Required
• Page Mode Capability
• CAS Controlled Output Allows Hidden Refresh
PIN
IlPD2118
IlPD2118·2
IlPD2118·3
ACCESS TIME
150 ns
120 ns
100 r1'S
RIW CYCLE
320 ns
270 ns
235 ns
RMWCYCLE
410 ns
345 ns
295 ns
PIN CONFIGURATION
NC
DIN
WE
RAS
AO
A2
Al
Vss
CAS
DOUT
A6
A3
A4
AS
NC
An·All
CAS
DIN
DOUT
WE
RAS
VDD,
Vss
PIN NAMES
ADDRESS INPUTS
COLUMN ADDRESS STROBE
DATA IN
DATA OUT
WRITE ENABLE
ROW ADDRESS STROBE
POWER (+SV)
GROUND
37
|
|
TIMING
WAVEFORMS
iJ)'CAP
READ CYCLE
p.PD2118
",,--,,@d--'-+---+r--d-+--i-----r-r------+-----
®
WRITE CYCLE
'"
@
'RAS
®
~;",@""---j
'C.H
'''"
~
.@i\\\ @
,
'=
){: XI Kf)""r- r--"""--j ..~t-
1--"""--1
"M",J(
COLUMN
,r-'~'-
@
,~,
-;:-'''~.
x: xI-@'~::"'" -""@~
I
'DHR
f--",--j
IT
I"~~
II
DoUT ~~ _ _ _ _ _--,;;;~,-----------------------
READ-MODI FY-WRITE CYCLE
----w @
'Awe
'flPW
Ir-,",--j
tCRP--j
~
~tACO =c-
@,\\' _611
r=:r-""'''"t-- tASC-r- ---j,,,"
AOORtSSES VII,
'"
){Qi» AO~~~SS K X
@
COU)MN
ADDRESS
X
'RWD
tACSr-
_ _ _ _ 'cwo
@WJl"
-''"'---I
'CRW
r-'""'-=Ut----'CWl
f--'.'--V
@'oo-j f-''®1
" "DOUT VOL
I
HIGH
IMPEDANce
)(L@OATAIN
VALID
r.=:--- 'CAe - - - - j Ii>
'"" ~
VALID
QATAOUT
DC
- p''
NOTES: See page 7.
41
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Information | Total 9 Pages | |
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