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PDF MCM62940B Data sheet ( Hoja de datos )
| Número de pieza | MCM62940B | |
| Descripción | 32K x 9 Bit BurstRAM Synchronous Static RAM | |
| Fabricantes | Motorola Semiconductors | |
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MOTOROLA
• SEMICONDUCTOR
TECHNICAL DATA
MCM62940B
Advance Information
32K x 9 Bit BurstRAMTM
Synchronous Static RAM
With Burst Counter and Self-Timed Write
The MCM62940B is a 294,912 bit synchronous static random access memory
designed to provide a burstable, high-performance, secondary cache for the MC68040
and PowerPCTM microprocessors. It is organized as 32,768 words of 9 bits, fabricated
using Motorola's high-performance silicon-gate CMOS technology. The device inte-
grates input registers, a 2-bit counter, high speed SRAM, and high drive capability out-
puts onto a single monolithic circuit for reduced parts count implementation of cache
data RAM applications. Synchronous design allows precise cycle control with the use
of an external clock (K). CMOS circuitry reduces the overall power consumption of the
integrated functions for greater reliability.
A2
Addresses (AO - A14), data inputs (DOO - D08), and all control signals,
A3
except output enable (<3), are clock (K) controlled through positive-edge-trig-
A4
gered noninverting registers.
AS
Bursts can be initiated with either transfer start processor (TSP) or transfer
A6
start cache controller (TSC) input pins. Subsequent burst addresses are gen-
erated internally by the MCM62940B (burst sequence imitates that of the
MC68040 and PowerPC) and controlled by the burst address advance (BAA)
input pin. The following pages provide more detailed information on burst con-
trols.
Write cycles are internally self-timed and are initiated by the rising edge of the
Vss
DOO
DOl
VSSO
VCCO
002
clock (K) input. This feature eliminates complex off-Chip write pulse generation
and provides increased flexibility for incoming signals.
The MCM62940B is packaged in a 44-pin plastic-leaded chip carrier (PLCC).
Multiple power and ground pins have been utilized to minimize effects induced
by output noise. Separate power and ground pins have been employed for
DOO - D08 to allow user-controlled output levels of 5 volts or 3.3 volts.
• Single 5 V ± 10% Power Supply
• Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility
• Fast Access limes: 11/12114/19/24 ns Max, Cycle limes: 15/20/20/25/30 ns Min
• Internal Input Registers (Address, Data, Control)
Internally Self-limed Write Cycle
• TSP, TSC, and BAA Burst Control Pins
• Asynchronous Output Enable Controlled Three-State Outputs
• Common Data Inputs and Data Outputs
• High Output Drive Capability: 85 pF per I/O
• High Board Density PLCC Package
• Fully TTL-Compatible
• Active High and Low Chip Select Inputs for Easy Depth Expansion
FN PACKAGE
44-LEAD PLCC
CASE 777
PIN ASSIGNMENT
8,...~ ol~lgl~ ~~~IDI-I-~>~ex~) 0~> ~
S 4 3 2 1 44 43 42 4140
39
38
37
36
35
34
33
32
31
16 30
17 29
18 19 20 21 2223 24 2526 2728
8 g 81:: 8~'~ ~I(j) ~ g
0>00> >
0>00
All
I IA12
A13
A14
VSS
D07
D06
VSSO
VCCO
DOS
D04
PIN NAMES
AO - A14 ............ Address Inputs
K ........................... Clock
W .............. Synchronous Write
G .................. Output Enable
SO, Sf ................ Chip Selects
BAA ........ Burst Address Advance
TSP, TSC ............ Transfer Start
DaO - Da8 . . . . . .. Data InpuVOutput
VCC ............ + 5 V Power Supply
Vcca ... Output Buffer Power Supply
VSS ...................... Ground
Vssa ........ Output Buffer Ground
All power supply and ground pins must
be connected for proper operation of the
device. VCc~ Vccaatalltimesincluding
power up.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
BurstRAM is a trademark of Motorola, Inc.
PowerPC is a trademark of IBM Corp.
MOTOROLA FAST SRAM DATA
MCM62940B
4·93
1 page  
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = ato + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference level. . . . . . . . . . . . . .. 1.5 V
Input Pulse levels .... . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0 to 3.0 V
Input Rise/Fall Time .................................... 3 ns
Output Timing Reference level . . . . . . . . . . . . . . . . . . . . . . . . .. 1.5 V
Output load ............ See Figure 1A Unless Otherwise Noted
READIWRITE CYCLE TIMING (See Notes 1, 2, and 3)
Symbol
629408-11 629408-12 629408-14 629408-19 629408-24
Parameter
Std Alt Min Max Min Max Min Max Min Max Min Max Unit Notes
Cycle Time
tKHKH tCYC 15 -
20 -
20 -
25 -
30 -
ns
Clock Access Time
tKHQV tCD -
11 -
12 -
14 -
19 -
24 ns
Output Enable to Output Valid tGlQV tOE -
5-
5-
6-
7-
7 ns
Clock High to Output Active tKHQX1 tDC1
6-
6-
6-
6-
6-
ns
Clock High to Output Change tKHQX2 tDC2
3-
3-
5-
5-
5 - ns
Output Enable to Output
Active
IGlQX toLZ
0-
0-
0-
0-
0-
ns
4
Output Disable to Q High-Z
tGHQZ toHZ -
6-
6-
6-
7-
7 ns
Clock High to Q High-Z
tKHQZ tez -
6-
6-
6-
6-
6 ns
Clock High Pulse Width
tKHKl tCH 5.5 -
7-
8-
9 - 11 - ns
Clock low Pulse Width
tKlKH
tCl 5.5 -
7-
8-
9-
11 -
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Select
tAVKH
ITSVKH
tDVKH
twvKH
tBAVKH
tSOVKH
tAS
tss
tDS
tws
2-
2-
3-
3-
3-
ns
tS1VKH
5
5
6
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Select
tKHAX
tKHTSX
tKHDX
tKHWX
tKHBAX
tKHSOX
tKHS1X
tAH
tSH
tDH
twH
2-
2-
2-
2-
2 - ns
6
NOTES:
1. A read cycle is defined by Vii high or TSP low for the setup and hold times. A write cycle is defined by Vii low and TSP high for the setup and
hold times.
.
2. All read and write cycle timings are referenced from K or G.
3. G is a don't care when Vii is sampled low.
4. Maximum access times are guaranteed for all possible MC68040 extemal bus cycles.
5. Transition is measured ± 500 mV from steady-state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.
6. This is a synchronous device. All addresses must meet the specified setup and hold times for ALL rising edges of clock (K) whenever TSP
or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL riSing edges of
K when the chip is selected.Chip select must be true (S1 low and SO high) at each rising edge of clock for the device (when TSP or TSC is
low) to remain enabled. Timings for S1 and SO are similar.
AC TEST LOADS
I f iOUTPUT
f- Zo= son -;
50 Q
5V
:dOUTPUT
255 n
+ 480n
5pF
(INCLUDING
SCOPE AND JIG)
Figure 1A
Figure 18
MOTOROLA FAST SRAM DATA
MCM62940B
4-97
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MCM62940B.PDF ] | |
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