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PDF 74LVC14A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC14A | |
| Descripción | LOW VOLTAGE CMOS HEX INVERTER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74LVC14A
LOW VOLTAGE CMOS HEX INVERTER
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: tPD = 5.0ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V (1.2V Data
Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 00
s LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
s ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LVC14A is a low voltage CMOS HEX
SCHMITT INVERTER fabricated with sub-micron
silicon gate and double-layer metal wiring C2MOS
technology. It is ideal for 1.65 to 3.6 VCC
operations and low power and low noise
applications.
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVC14AMTR
74LVC14ATTR
It can be interfaced to 5V signal environment for
inputs in mixed 3.3/5V system.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
Pin configuration and function are the same as
those of the 74LVC04A but the 74LVC14A has
hysteresis between the positive and negative
input threshold typically of 700mV.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 7
1/12
1 page  
74LVC14A
Table 8: AC Electrical Characteristics
Test Condition
Value
Symbol
Parameter
tPLH tPHL Propagation Delay
Time
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
VCC
CL RL ts = tr
(V) (pF) (Ω) (ns)
1.65 to 1.95 30 1000 2.0
2.3 to 2.7 30 500 2.0
2.7 50 500 2.5
3.0 to 3.6 50 500 2.5
2.7 to 3.6
-40 to 85 °C
Min.
1
Max.
10.5
7.0
6.0
5.0
1
-55 to 125 °C
Min.
1
Max.
14
9.1
7.5
6.4
1
Unit
ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics
Test Condition
Value
Symbol
Parameter
CIN Input Capacitance
CPD Power Dissipation Capacitance
(note 1)
VCC
(V)
1.8
2.5
3.3
fIN = 10MHz
TA = 25 °C
Min. Typ. Max.
4
37
38
42
Unit
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
5/12
5 Page 
Table 11: Revision History
Date
27-Jul-2004
Revision
7
Description of Changes
Ordering Codes Revision - pag. 1.
74LVC14A
11/12
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 74LVC14A.PDF ] | |
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