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PDF IDT8T73S208I Data sheet ( Hoja de datos )
| Número de pieza | IDT8T73S208I | |
| Descripción | LVPECL Clock Divider and Fanout Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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2.5V, 3.3V Differential LVPECL Clock IDT8T73S208I
Divider and Fanout Buffer
DATA SHEET
General Description
The IDT8T73S208I is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The IDT8T73S208I is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8T73S208I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are enabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVPECL outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1000MHz
• LVCMOS interface levels for the control inputs
• Individual output enable/disabled by I2C interface
• Output skew: 15ps (typical)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 0.182ps (typical)
• Full 2.5V and 3.3V supply voltages
• Available in Lead-free (RoHS 6) 32-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50Ω
fREF
÷1, ÷2,
÷4, ÷8
50Ω
VT
FSEL[1:0]
Pulldown (2)
2
SDA
SCL
ADR[1:0]
Pullup
Pullup
Pulldown (2)
2
I2C
8
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pin Assignment
24 23 22 21 20 19 18 17
FSEL1 25
IN 26
VT 27
nIN 28
VCC 29
SDA 30
SCL 31
ADR0 32
IDT8T73S208i
32-lead VFQFN
5mm x 5mm x 0.925mm
package body
NL Package, Top View
16 nQ5
15 Q5
14 nQ4
13 Q4
12 nQ3
11 Q3
10 nQ2
9 Q2
12345678
IDT8T73S208BNLI REVISION A OCTOBER 21, 2011
1
©2011 Integrated Device Technology, Inc.
1 page  
IDT8T73S208I Data Sheet
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND FANOUT BUFFER
Table 4C. DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VIN
VIH
VIH
VIL
VDIFF_IN
RIN
RIN_DIFF
Input Voltage Swing; NOTE 1
Input High Voltage
(IN, nIN)
Input High Voltage
(IN, nIN)
Input Low Voltage
(IN, nIN)
Differential Input Voltage Swing
Input Resistance
IN, nIN
Differential Input Resistance IN, nIN
VIN<=1V
VIN>1V
IN to VT
IN to nIN, VT = open
0.15
1.2
1.4
0
0.3
40 50
80 100
NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing diagram.
Maximum
VCC
VCC
VIH – 0.15
60
120
Units
V
V
V
V
V
Ω
Ω
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
VCCO – 1.102
VCCO – 1.802
0.60
VCCO – 0.95
VCCO – 1.6
0.65
Maximum
VCCO – 0.775
VCCO – 1.367
1.00
Units
V
V
V
Table 4E. LVPECL DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
VOH
VOL
VSWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO – 1.125
VCCO – 1.799
0.60
VCCO – 0.95
VCCO – 1.6
0.65
VCCO – 0.767
VCCO – 1.359
1.00
NOTE 1: Outputs terminated with 50Ω to VCCO – 2V.
Units
V
V
V
IDT8T73S208BNLI REVISION A OCTOBER 21, 2011
5
©2011 Integrated Device Technology, Inc.
5 Page 
IDT8T73S208I Data Sheet
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND FANOUT BUFFER
Parameter Measurement Information, continued
Part 1
nQx
Qx
Part 2
nQy
Qy
t sk(pp)
Part-to-Part Skew
nQ[0:7]
80%
20%
Q[0:7]
nQ[0:7]
tR
90%
10%
Q[0:7]
tR
Output Rise/Fall Time
nQ[0:7]
Q[0:7]
t PW
t
PERIOD
odc = t PW x 100%
t PERIOD
Output Duty Cycle/Pulse Width/Period
80%
tF
VSW I N G
20%
90%
tF
VSW I N G
10%
VIN VDIFF_IN
Differential Voltage Swing = 2 x Single-ended VIN
Single-Ended & Differential Input, Output Voltage Swing
IDT8T73S208BNLI REVISION A OCTOBER 21, 2011
11
©2011 Integrated Device Technology, Inc.
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet IDT8T73S208I.PDF ] | |
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