PDF AS4C128M8D3L Data sheet ( Hoja de datos )

Número de pieza	AS4C128M8D3L
Descripción	1Gb DDR3L
Fabricantes	Alliance Semiconductor
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No Preview Available ! 1Gb DDR3L – AS4C128M8D3L Revision History AS4C128M8D3L - 78-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Added "Backward compatible to VDD & VDDQ = 1.5V +/- 0.075V" - page 2 Updated Table 12. Recommended DC Operating Conditions – page 21 Added CL=5 & CL=6 to Table 18 – page 26 Date April 2014 August 2014 Confidential 1 Rev. 2.0 Aug. /2014 1 page 1Gb DDR3L – AS4C128M8D3L Figure 3. State Diagram This simplified State Diagram is intended to provide an overview of the possible state transitions and the commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die termination, and some other events are not captured in full detail. Power applied Power On Reset Procedure Initialization MRS,MPR, Write Leveling Self Refresh from any state RESET ZQCL MRS ZQ ZQCL,ZQCS Calibration Idle REF Refreshing ACT ACT = Active PRE = Precharge PREA = Precharge All MRS = Mode Register Set REF = Refresh RESET = Start RESET Procedure Read = RD, RDS4, RDS8 Read A = RDA, RDAS4, RDAS8 Write = WR, WRS4, WRS8 Write A = WRA, WRAS4, WRAS8 ZQCL = ZQ Calibration Long ZQCS = ZQ Calibration Short PDE = Enter Power-down PDX = Exit Power-down SRE = Self-Refresh entry SRX = Self-Refresh exit MPR = Multi-Purpose Register Automatic Sequence Command Sequence Active Power Down PDX PDE WRITE Writing WRITE A Writing WRITE A Activating Bank Activating WRITE Precharging Precharge Power Down READ READ READ READ A Reading READ A READ A Reading Confidential 5 Rev. 2.0 Aug. /2014 5 Page 1Gb DDR3L – AS4C128M8D3L  Reset Procedure at Stable Power The following sequence is required for RESET at no power interruption initialization. 1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time 10ns). 2. Follow Power-up Initialization Sequence step 2 to 11. 3. The Reset sequence is now completed. DDR3L SDRAM is ready for normal operation. Figure 5. Reset Procedure at Power Stable Condition CK# CK VDD VDDQ Ta Tb Tc Td Te Tf Tg Th Ti T=100ns tCKSRX T=500μs RESET# CKE COMMAND Tmin=10ns tIS tIS tXPR tMRD tMRD tMRD tDLLK tMOD Note 1 MRS MRS MRS MRS ZQCL Tj tZQinit Note 1 Tk VALID BA ODT RTT MR2 MR3 MR1 MR0 tIS Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW VALID tIS VALID NOTE 1. From time point “Td”until “Tk”NOP or DES commands must be applied between MRS and ZQCL commands. TIME BREAK Don't Care Confidential 11 Rev. 2.0 Aug. /2014 11 Page

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