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PDF AS4C128M16D3LB-12BCN Data sheet ( Hoja de datos )
| Número de pieza | AS4C128M16D3LB-12BCN | |
| Descripción | Double-data-rate architecture | |
| Fabricantes | Alliance Semiconductor | |
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AS4C128M16D3LB-12BCN
Revision History
2Gb AS4C128M16D3LB-12BCN - 96 ball FBGA PACKAGE
Revision Details
Rev 1.0 Preliminary datasheet
Date
Mar. 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
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Rev.1.0 Mar 2016
1 page  
AS4C128M16D3LB-12BCN
Pin Type
Function
TDQS, TDQS
Output
Termination Data Strobe : TDQS/TDQS is applicable for x8 DRAMs only. When enabled via Mode
Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS
that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide
the data mask function and TDQS is not used. x16 DRAMs must disable the TDQS function via mode
register A11 = 0 in MR1.
NC No Connect: No internal electrical connection is present.
VDDQ
Supply DQ power supply: 1.35V, 1.283 - 1.45V operational; compatible to 1.5+/- 0.075V operation.
VSSQ
Supply DQ Ground
VDD
Supply Power Supply: 1.35V, 1.283 - 1.45V operational; compatible to 1.5+/- 0.075V operation.
VSS
Supply Ground
VREFDQ
Supply Reference Voltage for DQ
VREFCA
Supply Reference Voltage for CA
ZQ Supply Reference Pin for ZQ calibration
NOTE : Input only pins ( BA0-BA2, A0-A14, RAS, CAS, WE, CS, CKE, ODT and RESET ) do not supply termination.
Confidential
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AS4C128M16D3LB-12BCN
Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and
CAS write latency (CWL). The Mode Register 2 is written by asserting low on CS, RAS, CAS, WE, high on
BA1, low on BA0 and BA2, while controlling the states of address pins according to the table below.
BA2 BA1 BA0
A14 - A11
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field
0*1 1
0
0*1
Rtt_WR 0*1 SRT ASR
CWL
0*1 Mode Register 2
A7 Self-refresh temperature range (SRT)
0 Normal operating temperature range
1 Extend temperature self-refresh (Optional)
A6 Auto Self-refresh (ASR)
0 Manual SR Reference (SRT)
1 ASR enable (Optional)
A10 A9
00
01
10
11
Rtt_WR *2
Dynamic ODT off
(Write does not affect Rtt value)
RZQ/4
RZQ/2
Reserved
BA1 BA0
00
01
10
11
MRS mode
MR0
MR1
MR2
MR3
A5 A4 A3 CAS write Latency (CWL)
000
5 (tCK(avg) ≥2.5ns)
0 0 1 6 (2.5ns >tCK(avg) ≥1.875ns)
0 1 0 7 (1.875ns>tCK(avg) ≥1.5ns)
0 1 1 8 (1.5ns>tCK(avg) ≥1.25ns)
1 0 0 9 (1.25ns >tCK(avg) ≥1.07ns)
1 0 1 10 (1.07ns >tCK(avg) ≥0.935ns)
110
Reserved
111
Reserved
* 1 : BA2, A0 ~ A2, A8, A11 ~ A14 are RFU and must be programmed to 0 during MRS.
* 2 : The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
Confidential
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Rev.1.0 Mar 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS4C128M16D3LB-12BCN.PDF ] | |
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