SC9256 Datasheet PDF - Silan Semiconductors
Part Number | SC9256 | |
Description | PLL FOR DIGITAL TUNING SYSTEM | |
Manufacturers | Silan Semiconductors | |
Logo | ||
There is a preview and SC9256 download ( pdf file ) link at the bottom of this page. Total 22 Pages |
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PLL FOR DIGITAL TUNING SYSTEM
DESCRIPTION
The SC9256 is phase-locked loop (PLL) LSIs for digital tuning
systems (DTS) with built in 2 modulus prescalers.
All functions ate controlled through 3 serial bus lines. These LSIs are
used to configure high-performance digital tuning system.
DIP-16-300-2.54
FEATURES
* Optimal for configuring digital tuning systems in high-fi tuners and
car stereos.
* Built-in prescalers. Operate at input frequency ranging from 30~150
MHz during FMIN input (with 2 modulus prescaler) and at
0.5~40MHz during AMIN input (with 2 modulus prescaler or direct
dividing).
* 16 bit programmable counter, dual parallel output phase
comparator, crystal oscillator and reference counter.
* 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be
used.
* 15 possible reference frequencies. ( When using 4.5MHz crystal)
* Built-in 20 bit general-purpose counter for such uses as measuring
intermediate frequencies (IFIN1 and IFIN2)
* High-precision (±0.55~±7.15µs) PLL phase error detection.
* Numerous general-purpose I/O pins for such uses as peripheral
circuit control.
* All functions controlled through 3 serial bus lines.
*CMOS structure with operating power supply range of
VDD=5.0±0.5V.
SOP-16-300-1.27
* 3 N-channel open-drain output
ports (OFF withstanding voltage:
12V) for such uses as control
signal output.
* Standby mode function (turns off
FM, AM and IF amps) to save
current consumption.
ORDERING INFORMATION
Device
SC9256
SC9256S
Package
DIP-16-300-2.54
SOP-16-300-1.27
BLOCK DIAGRAM
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 1 of 22
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SC9256
FUNCTION DESCRIPTION
Serial I/O ports
As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the
2 sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the
controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8
address bits and 24 data bits.
Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit
address and functions of each register.
These registers consist of 24 bits and are selected by an 8 bit address.
A list of the address assignment for each register is given below under register assignments.
Register
Address
Contents of 24 bits
No. of bit
PLL divisor setting
16
Input
register 1
D0H
Reference frequency setting
PLL input and mode setting
Crystal oscillator selection
4
2
2
total 24
General=purpose counter control (including lock detection bit
4
control)
I/O port and general-purpose counter switching bits
3
I/O-5/CLK pin switching bit
1
Input
register 2
D2H
DO pin control
Test bit
1
1
I/O port control (also used as general-purpose counter input
5
selection bits)
Output data
9
total 24
Output
register 1
D1H
General-purpose counter numeric data
Not used
22
2
total 24
Lock detection data
5
I/O port control data
5
Output
register 2
D3H
Output data
Input data (undefined during output port selection)
4
5
Not used
5
total 24
When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is
performed.
When the CLOCK signal falls for 9 times, the output data are latched in parallel in the output registers. The
data are subsequently output serially from the data pin.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
REV:1.1 2002.08.14
Page 5 of 22
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Information | Total 22 Pages | |
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