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PDF 74LVC373A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC373A | |
| Descripción | OCTAL D-TYPE LATCH | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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74LVC373A
OCTAL D-TYPE LATCH
HIGH PERFORMANCE
s 5V TOLERANT INPUTS
s HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V
s POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
s SYMMETRICAL OUTPUT IMPEDANCE:
)|IOH| = IOL = 24mA (MIN) at VCC = 3V
t(ss PCI BUS LEVELS GUARANTEED AT 24 mA
SOP
TSSOP
cs BALANCED PROPAGATION DELAYS:
utPLH ≅ tPHL
rods OPERATING VOLTAGE RANGE:
VCC(OPR) = 1.65V to 3.6V (1.2V Data
PRetention)
Table 1: Order Codes
PACKAGE
SOP
T&R
74LVC373AMTR
tes PIN AND FUNCTION COMPATIBLE WITH
le74 SERIES 373
TSSOP
74LVC373ATTR
os LATCH-UP PERFORMANCE EXCEEDS
s500mA (JESD 17)
bs ESD PERFORMANCE:
OHBM > 2000V (MIL STD 883 method 3015);
-MM > 200V
t(s)DESCRIPTION
cThe 74LVC373A is a low voltage CMOS OCTAL
uD-TYPE LATCH fabricated with sub-micron silicon
rodgate and double-layer metal wiring C2MOS
technology. It is ideal for 1.65 to 3.6 VCC
Poperations and low power and low noise
teapplications.
leThese 8 bit D-Type latch are controlled by a latch
enable input (LE) and an output enable input (OE).
soWhile the LE inputs is held at a high level, the Q
outputs will follow the data input precisely or
inversely. When the LE is taken low, the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8 outputs will be in a normal logic state (high or
low logic level) and while high level the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
ObFigure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 3
1/13
1 page  
74LVC373A
Table 9: Capacitive Characteristics
Symbol
Parameter
CIN Input Capacitance
CPD Power Dissipation Capacitance
(note 1)
Test Condition
VCC
(V)
1.8 fIN = 10MHz
2.5
3.3
Value
TA = 25 °C
Min.
Typ.
4
28
30
34
Max.
Unit
pF
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit)
t(s)Figure 3: Test Circuit
duct(s) - Obsolete ProducRT = ZOUT of pulse generator (typically 50Ω)
roTable 10: Test Circuit And Waveform Symbol Value
lete PSymbol
soCL
ObRL = R1
1.65 to 1.95V
30pF
1000Ω
2.3 to 2.7V
30pF
500Ω
VCC
2.7V
50pF
500Ω
3.0 to 3.6V
50pF
500Ω
VS
2 x VCC
2 x VCC
6V
7V
VIH VCC VCC 2.7V 3.0V
VM
VCC/2
VCC/2
1.5V
1.5V
VOH
VCC
VCC
3.0V
3.5V
VX
VOL + 0.15V
VOL + 0.15V
VOL + 0.3V
VOL + 0.3V
VY
VOH - 0.15V
VOH - 0.15V
VOH - 0.3V
VOH - 0.3V
tr = tr
<2.0ns
<2.0ns
<2.5ns
<2.5ns
5/13
5 Page 
74LVC373A
Tape & Reel TSSOP20 MECHANICAL DATA
DIM.
MIN.
mm.
TYP
MAX.
MIN.
inch
TYP.
MAX.
A 330 12.992
C 12.8
13.2 0.504
0.519
D 20.2
0.795
N 60
t(s)T
cAo 6.8
duBo 6.9
roKo 1.7
PPo 3.9
Obsolete Product(s) - ObsoleteP 11.9
2.362
22.4
7 0.268
7.1 0.272
1.9 0.067
4.1 0.153
12.1 0.468
0.882
0.276
0.280
0.075
0.161
0.476
11/13
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet 74LVC373A.PDF ] | |
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