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PDF 74AVC1T45 Data sheet ( Hoja de datos )

Número de pieza 74AVC1T45
Descripción Dual-supply voltage level translator/transceiver
Fabricantes NXP Semiconductors　
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74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Rev. 6 — 20 April 2016
Product data sheet
1. General description
The 74AVC1T45 is a single bit, dual supply transceiver with 3-state output that enables
bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction
control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can
be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for
translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and
3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH
on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to
A.
The device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at
GND level, both A and B are in the high-impedance OFF-state.
2. Features and benefits
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
500 Mbit/s (1.8 V to 3.3 V translation)
320 Mbit/s (< 1.8 V to 3.3 V translation)
320 Mbit/s (translate to 2.5 V or 1.8 V)
280 Mbit/s (translate to 1.5 V)
240 Mbit/s (translate to 1.2 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II

1 page




74AVC1T45 pdf
NXP Semiconductors
74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC(A)
VCC(B)
IIK
VI
IOK
VO
supply voltage A
supply voltage B
input clamping current
input voltage
output clamping current
output voltage
VI < 0 V
VO < 0 V
Active mode
Suspend or 3-state mode
[1]
[1][2][3]
[1]
0.5
0.5
50
0.5
50
0.5
0.5
+4.6 V
+4.6 V
- mA
+4.6 V
- mA
VCCO + 0.5 V
+4.6 V
IO output current
VO = 0 V to VCCO
- 50 mA
ICC
IGND
supply current
ground current
ICC(A) or ICC(B)
-
100
100 mA
- mA
Tstg storage temperature
Ptot
total power dissipation
Tamb = 40 C to +125 C
65
[4] -
+150
250
C
mW
[1] The minimum input voltage ratings and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] VCCO is the supply voltage associated with the output port.
[3] VCCO + 0.5 V should not exceed 4.6 V.
[4] For SC-88 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
For X2SON6 and XSON6 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 6.
Symbol
VCC(A)
VCC(B)
VI
VO
Tamb
t/V
Recommended operating conditions
Parameter
Conditions
supply voltage A
supply voltage B
input voltage
output voltage
Active mode
Suspend or 3-state mode
ambient temperature
input transition rise and fall rate VCCI = 0.8 V to 3.6 V
[1] VCCO is the supply voltage associated with the output port.
[2] VCCI is the supply voltage associated with the input port.
Min
0.8
0.8
0
[1] 0
0
40
[2] -
Max
3.6
3.6
3.6
VCCO
3.6
+125
5
Unit
V
V
V
V
V
C
ns/V
74AVC1T45
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 20 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 25

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74AVC1T45 arduino
NXP Semiconductors
74AVC1T45
Dual-supply voltage level translator/transceiver; 3-state
Table 13. Dynamic characteristics for temperature range 40 C to +125 C [1]
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9; for wave forms see Figure 7 and Figure 8
Symbol Parameter Conditions VCC(B)
Unit
1.2 V 0.1 V 1.5 V 0.1 V 1.8 V 0.15 V 2.5 V 0.2 V 3.3 V 0.3 V
Min Max Min Max Min Max Min Max Min Max
VCC(A) = 1.1 V to 1.3 V
tpd propagation A to B
delay
B to A
1.0 9.9 0.7 7.5 0.6 6.8 0.5 6.3 0.5 6.8 ns
1.0 9.9 0.8 8.8 0.7 8.5 0.6 8.0 0.5 7.9 ns
tdis disable time DIR to A 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 2.2 9.7 ns
DIR to B
2.2 9.2 1.8 7.4 2.0 7.6 1.7 6.9 2.4 8.0 ns
ten enable time DIR to A
DIR to B
- 19.1 - 16.2 - 16.1 - 14.9 - 15.9 ns
- 19.6 - 17.2 - 16.5 - 16.0 - 16.5 ns
VCC(A) = 1.4 V to 1.6 V
tpd propagation A to B
delay
B to A
1.0 8.8 0.7 6.0 0.6 5.1 0.5 4.1 0.5 3.9 ns
1.0 7.5 0.8 6.0 0.7 5.7 0.6 5.2 0.5 5.0 ns
tdis disable time DIR to A 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 1.6 7.0 ns
DIR to B
2.0 8.3 1.8 6.5 1.6 6.6 1.2 5.3 1.7 6.1 ns
ten enable time DIR to A
DIR to B
- 15.8 - 12.5 - 12.3 - 10.5 - 11.1 ns
- 15.8 - 13.0 - 12.1 - 11.1 - 10.9 ns
VCC(A) = 1.65 V to 1.95 V
tpd propagation A to B
delay
B to A
1.0 8.5 0.6 5.7 0.5 4.8 0.5 3.8 0.5 3.5 ns
1.0 6.8 0.7 5.1 0.5 4.9 0.5 4.3 0.5 4.1 ns
tdis disable time DIR to A 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 1.6 6.1 ns
DIR to B
1.8 8.5 1.8 6.3 1.4 6.4 1.0 5.0 1.5 5.8 ns
ten enable time DIR to A
DIR to B
- 15.3 - 11.4 - 11.3 - 9.3 - 9.9 ns
- 14.6 - 11.8 - 10.9 - 9.9 - 9.6 ns
VCC(A) = 2.3 V to 2.7 V
tpd propagation A to B
delay
B to A
1.0 8.0 0.5 5.2 0.5 4.3 0.5 3.3 0.5 2.9 ns
1.0 6.3 0.6 4.2 0.5 3.8 0.5 3.3 0.5 3.1 ns
tdis disable time DIR to A 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 1.5 4.7 ns
DIR to B
1.7 8.0 2.0 5.8 1.5 5.7 0.6 4.7 1.1 5.3 ns
ten enable time DIR to A
DIR to B
- 14.3 - 10.0 - 9.5 - 8.0 - 8.4 ns
- 12.7 - 9.9 - 9.0 - 8.0 - 7.6 ns
VCC(A) = 3.0 V to 3.6 V
tpd propagation A to B
delay
B to A
1.0 7.9 0.5 5.0 0.5 4.1 0.5 3.1 0.5 2.7 ns
1.0 6.8 0.6 4.0 0.5 3.5 0.5 2.9 0.5 2.7 ns
tdis disable time DIR to A 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 1.5 5.2 ns
DIR to B
1.7 7.9 0.7 6.1 0.6 6.1 0.7 4.6 1.7 5.2 ns
ten enable time DIR to A
DIR to B
- 14.7 - 10.1 - 9.6 - 7.5 - 7.9 ns
- 13.1 - 10.2 - 9.3 - 8.3 - 7.9 ns
[1] tpd is the same as tPLH and tPHL; tdis is the same as tPLZ and tPHZ; ten is the same as tPZL and tPZH.
ten is a calculated value using the formula shown in Section 13.4 “Enable times”
74AVC1T45
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 6 — 20 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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